Photonic semiconductor-insulator-semiconductor modulator and methods for forming the same

A photonic device, comprising:

• a first terminal comprising a p-type semiconductor, wherein the first terminal is a first three-dimensional structure extending along a first direction and having a first overlapping portion in a first cross-sectional plane perpendicular to the first direction;
• a second terminal comprising an n-type semiconductor, wherein the second terminal is a second three-dimensional structure extending along the first direction and having a second overlapping portion in the first cross-sectional plane perpendicular to the first direction;
• a capacitor dielectric layer disposed between the first terminal and the second terminal;
• and
• a cladding dielectric layer surrounding the first terminal and the second terminal,
• wherein the first overlapping portion and the second overlapping portion are arranged in an interlocking configuration comprising an overlapping region such that, in the overlapping region, the first terminal and the second terminal are further overlapping in a second cross-sectional plane that is perpendicular to the first cross-sectional plane,
• wherein each of the first overlapping portion and the second overlapping portion are folded an integer number (m) of times such that the overlapping region comprises an alternating stack of m+1 first folded segments of the first terminal and m+1 second folded segments of the second terminal, wherein m is greater than or equal to 1, and
• wherein the overlapping region is configured as an optical transmission line in which the first direction is an optical propagation direction.

A method of forming a photonic device, comprising:

• depositing, over a substrate, alternating layers of a first-conductivity-type semiconductor and a second-conductivity-type semiconductor along with capacitor dielectric layers separating adjacent alternating layers;
• sequentially, upon completion of a deposition process for each of the alternating layers, performing an etching operation to reduce a width of each of the alternating layers;
• and
• forming, for each subsequent layer of a given conductivity-type semiconductor, a vertical edge portion of the given conductivity-type semiconductor that connects the subsequent layer with a previously deposited layer of the given conductivity-type semiconductor,
• wherein a plurality of connected first-conductivity-type semiconductor layers forms a first terminal having a first overlapping portion in a first cross-sectional plane perpendicular to a first direction,
• wherein a plurality of connected second-conductivity-type semiconductor layers forms a second terminal having a second overlapping portion in the first cross-sectional plane, and
• wherein the first overlapping portion and the second overlapping portion are arranged in an interlocking configuration comprising an overlapping region such that, in the overlapping region, the first terminal and the second terminal are further overlapping in a second cross-sectional plane that is perpendicular to the first cross-sectional plane.