Power rails for stacked semiconductor device

A semiconductor device, comprising:

• first and second stacks of semiconductor layers on a first surface of a substrate, wherein the first stack of semiconductor layers is stacked over the second stack of semiconductor layers;
• an epitaxial layer between the first and second stacks of semiconductor layers;
• a gate structure surrounding the first and second stacks of semiconductor layers;
• a source/drain (S/D) region in contact with the second stack of semiconductor layers and the epitaxial layer;
• and
• a S/D contact structure on a second surface of the substrate and connected to the S/D region, wherein the second surface is opposite to the first surface.

A semiconductor device, comprising:

• first and second stacks of semiconductor layers on a first surface of a substrate, wherein the first stack of semiconductor layers is stacked over the second stack of semiconductor layers;
• a dielectric structure between the first and second stacks of semiconductor layers;
• an epitaxial layer on the dielectric structure;
• a first source/drain (S/D) region on the epitaxial layer and in contact with the first stack of semiconductor layers;
• a second S/D region in contact with the second stack of semiconductor layers, wherein the dielectric structure is in contact with top surfaces of the second stacks of semiconductor layers and the second S/D region;
• and
• first and second S/D contact structures on a second surface of the substrate, wherein:
• the second surface is opposite to the first surface;
• the first S/D contact structure is connected to the first S/D region;
• and
• the second S/D contact structure is connected to the second S/D region.