Semiconductor device with improved mechanical stress resistance

A semiconductor device, comprising:

• a silicon semiconductor substrate having a first doped region of a first doping type, and a second doped region of a second doping type,
• wherein the silicon semiconductor substrate physically expands or contracts in response to a temperature change;
• wherein the first doped region is beneath and immediately adjacent to in a first direction, the second doped region;
• wherein the first doped region and the second doped region form a P-N Zener diode junction region having a Zener breakdown voltage;
• wherein the Zener breakdown voltage drifts in response to the temperature change;
• and
• an additional polysilicon layer coupled above and covering the P-N Zener diode junction region,
• wherein the additional polysilicon layer physically expands or contracts in response to the temperature change substantially same as does the silicon semiconductor substrate,
• wherein in response to coupling of the additional polysilicon layer to the silicon semiconductor substrate, the Zener breakdown voltage drift is reduced in response to the temperature change;
• a second additional polysilicon layer that has been deposited above the additional polysilicon layer, wherein the additional polysilicon layer is wider in the second direction than the second additional polysilicon layer;
• wherein the second additional polysilicon layer also has similar mechanical properties as the silicon semiconductor substrate and covers at least 50% of the P-N Zener diode junction region;
• wherein a bottom surface of the second additional polysilicon layer is electrically insulated from a top surface of the additional polysilicon layer;
• a first electrical contact coupled to the first doped region;
• a second electrical contact coupled to the second doped region;
• a first electrical conductor electrically connecting the second electrical contact to the additional polysilicon layer;
• and
• a second electrical conductor electrically connecting the second electrical contact to the second additional polysilicon layer.