RRAM cell structure and fabrication method therefor

A fabrication method for a resistive random-access memory (RRAM) cell structure, wherein the RRAM cell structure comprises a first transistor and a second transistor which are connected in parallel and a resistive switching device connected with the first transistor and the second transistor commonly;

• wherein,
• the first transistor is set with a first gate, a first source and a first drain, a first control signal is applied to the first gate, and a first source signal is applied to the first source;
• the second transistor is set with a second gate, a second source and a second drain, a second control signal is applied to the second gate, and a second source signal is applied to the second source;
• the first drain is connected with the second drain, which are commonly connected to one terminal of the resistive switching device, and a bit signal is applied to another terminal of the resistive switching device, the fabrication method comprising:
• S1:
• providing a planar silicon substrate, defining a device region of the first transistor and the second transistor on the silicon substrate, and forming a raised cuboid on the silicon substrate in the device region;
• S2:
• forming the first drain of the first transistor and the second drain of the second transistor on the top surface of the raised cuboid, connecting the first drain and the second drain, and forming the first source of the first transistor and the second source of the second transistor respectively on the semiconductor substrate adjacent to the two sides of the raised cuboid;
• S3:
• forming the first gate dielectric layer of the first transistor and the second gate dielectric layer of the second transistor respectively on each of the two sides of the raised cuboid and the surface of the semiconductor substrate adjacent to the two sides of the raised cuboid;
• S4:
• forming a first sidewall gate of the first transistor and a second sidewall gate of the second transistor respectively on the first gate dielectric layer and the second gate dielectric layer on each of the two sides of the raised cuboid;
• and
• S5:
• forming a dielectric layer on the silicon substrate, forming back-end metal layers in the dielectric layer, and forming a resistive switching stack of a resistive switching device above the first drain and the second drain, thus forming the RRAM cell structure;
• wherein, using a standard ion implantation process in CMOS technique, performing ion implantation processes with different types and doses to the first drain and the second drain, the first source and the second source and the first gate and the second gate respectively.

A fabrication method for a resistive random-access memory (RRAM) cell structure, wherein the RRAM cell structure comprises a first transistor and a second transistor which are connected in parallel and a resistive switching device connected with the first transistor and the second transistor commonly;

• wherein,
• the first transistor is set with a first gate, a first source and a first drain, a first control signal is applied to the first gate, and a first source signal is applied to the first source;
• the second transistor is set with a second gate, a second source and a second drain, a second control signal is applied to the second gate, and a second source signal is applied to the second source;
• the first drain is connected with the second drain, which are commonly connected to one terminal of the resistive switching device, and a bit signal is applied to another terminal of the resistive switching device, the fabrication method comprising:
• S1:
• providing a planar silicon substrate, defining a device region of the first transistor and the second transistor on the silicon substrate, and forming a raised cuboid on the silicon substrate in the device region;
• S2:
• forming the first drain of the first transistor and the second drain of the second transistor on the too surface of the raised cuboid, connecting the first drain and the second drain, and forming the first source of the first transistor and the second source of the second transistor respectively on the semiconductor substrate adjacent to the two sides of the raised cuboid;
• S3:
• forming the first gate dielectric layer of the first transistor and the second gate dielectric layer of the second transistor respectively on each of the two sides of the raised cuboid and the surface of the semiconductor substrate adjacent to the two sides of the raised cuboid;
• S4:
• forming a first sidewall gate of the first transistor and a second sidewall Pate of the second transistor respectively on the first gate dielectric layer and the second gate dielectric layer on each of the two sides of the raised cuboid;
• and
• S5:
• forming a dielectric layer on the silicon substrate, forming back-end metal layers in the dielectric layer, and forming a resistive switching stack of a resistive switching device above the first drain and the second drain, thus forming the RRAM cell structure;
• wherein, forming the first gate dielectric layer and the second gate dielectric layer comprises:
• S31:
• forming a thick gate dielectric layer on the top surface and both sides of the raised cuboid and on the surface of the semiconductor substrate adjacent to the two sides of the raised cuboid;
• S32:
• removing the thick gate dielectric layer on the second transistor;
• S33:
• forming a thin gate dielectric layer on the top surface and both sides of the raised cuboid and on the surface of the semiconductor substrate adjacent to the two sides of the raised cuboid.