Memory device and method for manufacturing memory device

A memory device, comprising:

• a substrate, and a plurality of first capacitors embedded in the substrate;
• a plurality of first vertical transistors and a plurality of second vertical transistors, wherein the plurality of first vertical transistors and the plurality of second vertical transistors are arranged on the substrate, and wherein each of the plurality of first vertical transistors is electrically connected to a respective one of the plurality of first capacitors, wherein each of the plurality of first vertical transistors comprises a first source/drain region, a channel region and a second source/drain region which are arranged from bottom to top, and each of the plurality of second vertical transistors comprises a first source/drain region, a channel region and a second source/drain region which are arranged from bottom to top, wherein the first source/drain region of each of the plurality of first vertical transistors is electrically connected to the respective one of the plurality of first capacitors, and the second source/drain region of each of the plurality of second vertical transistors is electrically connected to a respective one of the plurality of second capacitors;
• and
• a plurality of second capacitors arranged on the plurality of first vertical transistors and the plurality of second vertical transistors, wherein each of the plurality of second capacitors is electrically connected to a respective one of the plurality of second vertical transistors;
• a plurality of first bit lines extending in a first direction, wherein each of the plurality of first bit lines is arranged on the substrate and arranged around the first source/drain region of a respective one of the plurality of second vertical transistors, and the first source/drain region of a respective one of the plurality of second vertical transistors penetrates through a respective one of the plurality of first bit lines;
• a plurality of second bit lines extending in the first direction, wherein each of the plurality of second bit lines is arranged around the second source/drain region of a respective one of the plurality of first vertical transistors, and the second source/drain region of a respective one of the plurality of first vertical transistors penetrates through a respective one of the plurality of second bit lines.