US 12,501,600 B2Granted

SRAM cell structure

AssigneesInvention And Collaboration Laboratory Pte. Ltd., Etron Technology, Inc.

InventorsChao-Chun Lu, Li-Ping Huang, Juang-Ying Chueh

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Abstract

A SRAM cell structure includes a plurality of transistors, a set of contacts, a word-line, a bit-line, a VDD contacting line and a VSS contacting line. The plurality of transistors include n transistors, wherein n is a positive integral less than 6. The set of contacts are coupled to the plurality of transistors. The word-line is electrically coupled to the plurality of transistors. The bit-line and a bit line bar are electrically coupled to the plurality of transistors. The VDD contacting line is electrically coupled to the plurality of transistors. The VSS contacting line is electrically coupled to the plurality of transistors. Wherein as a minimum feature size of the SRAM cell structure gradually decreases from 28 nm, an area size of the SRAM cell in terms of square of the minimum feature size (λ) is the same or substantially the same.

Claims25

Dependent claims

A SRAM cell structure, comprising:

a substrate, having an original horizontal surface;
a plurality of transistors including n transistors formed in the substrate, wherein n is a positive integral less than 6;
wherein one of the n transistors comprises a gate structure, a source region and, a drain region and a localized isolation extending under the source region or the drain region but not extending under the gate structure, and a shallow trench isolation (STI) region surrounds the one transistor;
wherein a top surface of the STI region is higher than the original horizontal surface;
a set of contacts coupled to the plurality of transistors;
a word-line electrically coupled to the plurality of transistors;
a bit-line and a bit line bar electrically coupled to the plurality of transistors;
a VDD contacting line electrically coupled to the plurality of transistors;
a tunneling structure disposed between the VDD contacting line and the plurality of transistors;
and
a VSS contacting line electrically coupled to the plurality of transistors;
wherein as a minimum feature size of the SRAM cell structure is between 28 nm and 20 nm, an area size of the SRAM cell structure in terms of square of the minimum feature size (λ) is less than 100λ2;
or as the minimum feature size of the SRAM cell structure less than 20 nm and not less than 10 nm, the area size of the SRAM cell structure in terms of square of the minimum feature size (λ) is less than 200λ2;
or as the minimum feature size of the SRAM cell structure less than 10 nm and not less than 5 nm, the area size of the SRAM cell structure in terms of square of the minimum feature size (λ) is less than 300λ2.

11 more elements

A SRAM cell structure comprising a set of SRAM cells, comprising:

a substrate, having an original horizontal surface;
a first SRAM cell comprising:
a first pair of cross-coupled transistors formed in the substrate, wherein one of the first pair of cross-coupled transistors comprises a gate structure, a source region and a drain region and a localized isolation extending under the source region or the drain region but not extending under the gate structure, and a shallow trench isolation (STI) region surrounds the source region and the drain region;
wherein a top surface of the STI region is higher than the original horizontal surface;
a first VDD contacting line electrically coupled to the first pair of cross-coupled transistors;
and
a first VSS contacting line electrically coupled to the first pair of cross-coupled transistors;
a first tunneling structure disposed between the first VDD contacting line and the first pair of cross-coupled transistors;
a second SRAM cell comprising:
a second pair of cross-coupled transistors;
a second VDD contacting line electrically coupled to the second pair of cross-coupled transistors;
and
a second VSS contacting line electrically coupled to the second pair of cross-coupled transistors;
and
a second tunneling structure disposed between the second VDD contacting line and the second pair of cross-coupled transistors.

12 more elements

Dependencies are inferred from the claim text.

Facts

Application: 17/588,509Filed 31 Jan 2022 · us provisional application
Priority: 4 Oct 2021
Published: US 2023/0106517 A16 Apr 2023
Granted: 16 Dec 2025
Term ends: Not estimatedThe source records don’t support an estimate.

Classification8 codes

G11C 11/412
Forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt…
H10B 10/12
Static random access memory [SRAM] devices: comprising a MOSFET load element
H10D 8/70
Diodes: tunnel-effect diodes
H10W 20/427
Characterised by their conductive parts: power or ground buses