Image processing device for controlling pixel output level and operating method thereof

An image sensor comprising:

• a first pixel group comprising a first transfer transistor, a first reset transistor, and a first select transistor, the first pixel group being configured to:
• generate a first reset signal and output the first reset signal through a first column line, and
• generate a first image signal and output the first image signal through the first column line during a first time period;
• and
• a second pixel group comprising a second transfer transistor, a second reset transistor, and a second select transistor, the second pixel group being configured to:
• generate a second reset signal and output the second reset signal through the first column line during a second time period different from the first time period, and
• generate a second image signal and output the second image signal through the first column line during the second time period,
• wherein the second pixel group is configured to turn on the second select transistor during the first time period,
• wherein the first time period is from time point of generating the first reset signal to time point of outputting the first image signal, and
• wherein the second time period is from time point of generating the second reset signal to time point of outputting the second image signal.

An image sensor comprising:

• a first pixel group configured to:
• generate a first reset signal output the first reset signal through a first column line during a first time period, and
• generate a first image signal and output the first image signal through the first column line during the first time period;
• and
• a second pixel group configured to:
• generate a second reset signal and output the second reset signal through the first column line during a second time period different from the first time period, and
• generate a second image signal and output the second image signal through the first column line during the second time period,
• wherein the first time period is from time point of generating the first reset signal to time point of outputting the first image signal, and
• wherein the second time period is from time point of generating the second reset signal to time point of outputting the second image signal, and
• wherein the second pixel group is configured output a third reset signal through the first column line during the first time period.