Command address fault detection
AssigneeMicron Technology, Inc.
InventorsAaron P. Boehm, Melissa I. Uribe
Life of this patent
Estimating the term…
Abstract
Implementations described herein relate to command address fault detection. A memory device may receive, from a host device via a command address (CA) bus, a plurality of bits associated with a command signal or an address signal. The CA bus may be configured for communicating command signals and address signals between the memory device and the host device. The memory device may generate one or more parity bits based on the plurality of bits. The one or more parity bits may be generated using a parity generation process that is common to the memory device and the host device. The memory device may transmit, to the host device, the one or more parity bits.
Claims20
A memory device, comprising:
- one or more components configured to:
- receive, from a host device via a command address bus, a command address word that includes a plurality of bits;
- generate one or more parity bits based on applying a parity generation process to the command address word that is received via the command address bus;
- and
- transmit, to the host device and via a unidirectional pin, an indication of the one or more parity bits.
A system, comprising:
- a host device configured to:
- generate a command address word that includes a plurality of bits;
- transmit the command address word to a memory device via a command address bus;
- generate a first set of parity bits based on applying a parity generation process to the command address word;
- and
- compare the first set of parity bits and a second set of parity bits generated by the memory device;
- and
- the memory device, wherein the memory device is configured to:
- generate the second set of parity bits based on applying the parity generation process to the command address word;
- and
- transmit, to the host device and via a unidirectional pin, an indication of the second set of parity bits.
A method performed by a memory device, comprising:
- receiving, from a host device via a command address bus, a command address word that includes a plurality of bits;
- generating one or more parity bits based on applying a parity generation process to the command address word that is received via the command address bus;
- and
- transmitting, to the host device and via a unidirectional pin, an indication of the one or more parity bits.
Dependencies are inferred from the claim text.