Methods and apparatus to calibrate analog-to-digital converters

An apparatus comprising:

• time domain converter circuitry having a first input, a second input, a trim input, and an output, wherein differences between timing of the first and second inputs of the time domain converter circuitry represent a first delay;
• first comparator circuitry having a first input, a second input, and an output, the first input of the first comparator circuitry coupled to the first input of the time domain converter circuitry;
• second comparator circuitry having a first input, a second input, and an output, the first input of the second comparator circuitry coupled to the second input of the time domain converter circuitry;
• third comparator circuitry having a first input, a second input, and an output, the first input of the third comparator circuitry coupled to the second input of the first comparator circuitry, the second input of the third comparator circuitry coupled to the second input of the second comparator circuitry, wherein differences between timing of the first and second inputs of the time domain converter circuitry represent a second delay;
• and
• trim circuitry having a first input, a second input, a third input, and an output, the first input of the trim circuitry coupled to the output of the first comparator circuitry, the second input of the trim circuitry coupled to the output of the second comparator circuitry, the third input of the trim circuitry coupled to the output of the third comparator circuitry, the output of the trim circuitry coupled to the trim input of the time domain converter circuitry.

An apparatus comprising:

• time domain converter circuitry configured to determine a digital value that represents a first delay, the first delay being a delay between a first signal and a second signal;
• comparator circuitry coupled to the time domain converter circuitry, the comparator circuitry configured to compare the first delay to a second delay;
• and
• trim circuitry coupled to the time domain converter circuitry and the comparator circuitry, the trim circuitry is configured to adjust the time domain converter circuitry responsive to the digital value and the comparison.