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US 12,500,592 B2Granted
Device and method for time skew calibration of multi channel ADC
AssigneeSTMicroelectronics International N.V.
InventorsAnkur Bal, Jeet Narayan Tiwari
Life of this patent
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Abstract
An integrated circuit includes a plurality of ADC channels. During a calibration process of the ADC channels, the integrated circuit utilizes derivative filters to calculate a phase difference between the ADC channels. During a calibration process, the integrated circuit utilizes clock phase alignment circuits to align the phases of the ADC channels based on the outputs of the derivative filters.
Claims20
An integrated circuit, comprising:
- a first analog-to-digital converter channel having an input and an output;
- a second analog-to-digital converter channel having an input and an output;
- a phase detection circuit including:
- a first input coupled to the output of the first analog-to-digital converter channel;
- a second input coupled to the output of the second analog-to-digital converter channel;
- an output;
- a derivative filter coupled between the output and the first and second inputs, wherein the phase detection circuit is configured to determine a time difference between peaks in an output of the first analog-to-digital converter channel and an output of the second analog-to-digital channel based on the derivative filter;
- and
- a clock phase adjustment circuit configured to adjust a phase of a clock signal provided to the second analog-to-digital converter channel based on the time difference.
6 more elements
A method, comprising:
- generating, with a first analog-to-digital converter channel of an integrated circuit, a first output signal;
- generating, with a second analog-to-digital converter channel of the integrated circuit, a second output signal;
- generating, with a derivative filter, a derivative signal indicating a phase difference between the first output signal and the second output signal;
- determining, with a phase adjustment circuit, a time difference between peaks in an output of the first analog-to-digital converter channel and an output of the second analog-to-digital channel based on the derivative filter;
- and
- generating an adjusted clock signal by adjusting a phase of a clock signal provided to the second analog-to-digital converter channel based on the time difference.
3 more elements
A method, comprising:
- providing an analog test signal to a first analog-to-digital converter channel of an integrated circuit and to a plurality of second analog-to-digital converter channels of the integrated circuit;
- generating, with the first analog-to-digital converter channel, a first output signal based on the analog test signal;
- generating, with each second analog-to-digital converter channel, a respective second output signal based on the analog test signal;
- receiving the first output signal with each of a plurality of derivative filters;
- receiving, with each derivative filter, the second output signal of a respective second analog-to-digital converter;
- determining, with a phase adjustment circuit, a time difference between peaks in an output of the first analog-to-digital converter channel and an output of the second analog-to-digital channel based on at least one of the derivative filters;
- and
- generating an adjusted clock signal by adjusting a phase of a clock signal provided to the second analog-to-digital converter channel based on the time difference.
5 more elements
Dependencies are inferred from the claim text.