Fast-locking phase-locked loop, frequency divider, and communication device
AssigneeHangzhou Geo-chip Technology Co., Ltd.
InventorsYanping Zhou, Chun Geik Tan, Ruili Wu
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AssigneeHangzhou Geo-chip Technology Co., Ltd.
InventorsYanping Zhou, Chun Geik Tan, Ruili Wu
Estimating the term…
The present disclosure provides a phase-locked loop, a frequency divider and a communication device that enable fast locking. The phase-locked loop comprises a phase frequency detector, a charge pump, a loop filter, a voltage-controlled oscillator, a fast-locking control unit and a frequency divider, wherein the frequency divider comprises a plurality of cascaded frequency division units and a reset/set control circuit, the reset/set control circuit being configured to receive the reset signal outputted by the fast-locking control unit, and in response to transition of the reset signal from a low level to the high level, change a state code combination composed of respective state codes of the cascaded frequency division units from the first state to the second state, to cause transition of a feedback signal outputted by the frequency divider from the low level to the high level. With the frequency divider and phase-locked loop, fast locking can be achieved.
A fast-locking phase-locked loop, comprising a phase frequency detector, a charge pump, a loop filter, a voltage-controlled oscillator, a fast-locking control unit and a frequency divider,
A frequency divider for a fast-locking phase-locked loop, the frequency divider comprising a plurality of cascaded frequency division units and a reset/set control circuit, the reset/set control circuit being configured to, in response to transition of a reset signal from a low level to a high level, change a state code combination composed of respective state codes of the cascaded frequency division units from a first state to a second state through a reset/set operation, to cause transition of a feedback signal outputted by the frequency divider from the low level to the high level, wherein the reset signal transitions from a low level to a high level in response to a phase-locking enable signal and a rising edge of a reference clock.
Dependencies are inferred from the claim text.