Phase-locked loop circuit
AssigneeMediaTek Singapore Pte. Ltd.
InventorsMing Wang, Kun Lan, Cong Liu
Life of this patent
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AssigneeMediaTek Singapore Pte. Ltd.
InventorsMing Wang, Kun Lan, Cong Liu
Estimating the term…
A PLL circuit generates an output signal having an output frequency and includes a voltage-to-current conversion circuit, a frequency compensation circuit, and an ICO. The voltage-to-current conversion circuit is configured to generate a first control current according to a control voltage, wherein the control voltage is generated according to a reference signal and a feedback signal derived from the output signal. The frequency compensation circuit is configured to generate a second control current according to the control voltage. The ICO generates the output signal according to an oscillation current, wherein the oscillation current is a sum of the first control current and the second control current. In response to the frequency compensation circuit detecting that the control voltage is out of a predetermined range, the second control current is controlled to be negatively correlated with the output frequency.
A phase-locked loop (PLL) circuit generating an output signal with an output frequency, comprising:
Dependencies are inferred from the claim text.