Semiconductor device having fuse array
AssigneeMicron Technology, Inc.
InventorsYasushi Matsubara, Minoru Someya
Life of this patent
Estimating the term…
Abstract
An apparatus includes a memory chip including a plurality of fuse units, and a controller chip. Each fuse unit includes a fuse array having a plurality of fuse cells, a first register, and a second register. The controller is configured to set the fuse address in the second register included in selected one or more of the plurality of fuse units, set the match signal in the first register included in the selected one or more of the plurality of fuse units, and send a blow signal to the memory chip. Each of the selected one or more of the plurality of fuse units is configured to blow one of the plurality of fuse cells selected by the fuse address stored in the second register responsive to the blow signal.
Claims20
An apparatus comprising:
- a first memory chip including a plurality of first fuse units;
- and
- a controller chip coupled to the first memory chip,
- wherein each of the plurality of first fuse units includes:
- a fuse array having a plurality of fuse cells;
- a first register configured to store a match signal;
- and
- a second register configured to store a fuse address of one of the plurality of fuse cells,
- wherein the controller chip is configured to
- select one or more of the plurality of first fuse units;
- set the fuse address in the second register included in the selected one or more of the plurality of first fuse units;
- control the first memory chip to set the match signal in the first register included in the selected one or more of the plurality of first fuse units;
- and
- send a blow signal to the first memory chip, and
- wherein each of the selected one or more of the plurality of first fuse units is configured to blow one of the plurality of fuse cells selected by the fuse address stored in the second register responsive to the blow signal.
An apparatus comprising:
- a first memory chip including a first fuse unit;
- a second memory chip including a second fuse unit;
- and
- a controller chip that controls the first and second memory chips,
- wherein the first fuse unit includes:
- a first fuse array having a plurality of first fuse cells;
- and
- a first register configured to store a first fuse address of one of the plurality of first fuse cells,
- wherein the second fuse unit includes:
- a second fuse array having a plurality of second fuse cells;
- and
- a second register configured to store a second fuse address of one of the plurality of second fuse cells,
- wherein the controller chip is configured to
- set the first fuse address in the first register;
- set the second fuse address in the second register;
- and
- send a blow signal to the first and second memory chips in parallel,
- wherein the first fuse unit is configured to blow one of the plurality of first fuse cells selected by the first fuse address stored in the first register responsive to the blow signal, and
- wherein the second fuse unit is configured to blow one of the plurality of second fuse cells selected by the second fuse address stored in the second register responsive to the blow signal.
An apparatus comprising:
- a plurality of memory units;
- and
- a controller chip that controls the plurality of memory units,
- wherein each of the plurality of memory units includes:
- a memory cell array having a plurality of memory cells;
- and
- a fuse unit configured to store a memory address of a defective one of the plurality of memory cells,
- wherein the fuse unit includes:
- a fuse array having a plurality of fuse cells;
- a first register storing a match signal;
- and
- a second register storing a fuse address of one of the plurality of fuse cells,
- wherein the controller chip is configured to control the memory chips to set the match signal in the first register included in one of more of a plurality of fuse units including the fuse unit, set the fuse address in the second register included in the one or more of the plurality of fuse units in which the match signal is stored in the first register, and send a blow signal to the one or more of the plurality of fuse units in parallel, and
- wherein each of the plurality of fuse units in which the match signal is stored in the first register is configured to blow one of the plurality of fuse cells selected by the fuse address stored in the second register responsive to the blow signal.
Dependencies are inferred from the claim text.