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US 12,499,967 B2Granted
Row repair circuitry
AssigneeArm Limited
InventorsAndy Wangkun Chen, Khushal Gelda, Ramesh Manohar, Teresa Louise McLaurin, Prashant Mohan Kulkarni
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Abstract
Various implementations described herein are directed to a device having a bank of bitcells split into a plurality of portions including a first row slice of the bitcells and a second row slice of the bitcells. Also, the device may have control circuitry configured to access and repair a first bitcell in the first row slice with a first row address and a second bitcell in the second row slice with a second row address that is different than the first row address.
Claims20
A device comprising:
- a bank of bitcells split into a plurality of portions including a first row slice of the bitcells and a second row slice of the bitcells;
- first redundancy bitcells disposed horizontally adjacent to the first row slice;
- second redundancy bitcells disposed horizontally adjacent to the second row slice;
- and
- control circuitry configured to:
- access a first bitcell in the first row slice using a first row address to enable repair of the first bitcell using the first redundancy bitcells;
- and
- access a second bitcell in the second row slice using a second row address that is different than the first row address to enable repair of the second bitcell using the second redundancy bitcells.
5 more elements
A device comprising:
- a first bank having first bitcells partitioned into a plurality of portions including a first row slice of the first bitcells and a second row slice of the first bitcells;
- a second bank having second bitcells partitioned into another plurality of portions including a third row slice of the second bitcells and a fourth row slice of the second bitcells;
- and
- control circuitry disposed vertically between the first row slice and the second row slice, disposed vertically between the third row slice and the fourth row slice, the control circuitry configured to:
- access two different first bitcells in the first bank using a first pair of different addresses to enable repair of two different first bitcells using redundancy bitcells;
- and
- access two different second bitcells in the second bank using a second pair of different addresses to enable repair of two different second bitcells using redundancy bitcells.
4 more elements
A method comprising:
- splitting a bank of bitcells into a plurality of portions including a first row slice and a second row slice;
- accessing a first bitcell in the first row slice using a first address;
- accessing a second bitcell in the second row slice using a second address;
- repairing the first bitcell in the first row slice using first redundancy bitcells disposed horizontally adjacent to the first row slice;
- and
- repairing the second bitcell in the second row slice using second redundancy bitcells disposed horizontally adjacent to the second row slice.
3 more elements
Dependencies are inferred from the claim text.