Glitch detection
AssigneeMicron Technology, Inc.
InventorsNiccolò Izzo, David Hulton, Tamara Schmitz, Angelo Alberto Rovelli, Craig A. Jones, Danilo Caraccio
Life of this patent
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Abstract
A method can include performing at least one glitch resistance operation and detecting, by a circuit included in a glitch detector coupled via a connection matrix to a first processing unit, an indication of a glitch on a memory system. The method can include notifying, via the connection matrix, at least a second processing unit of the detected indication of the glitch. The method can include subsequent to notifying at least the second processing unit, transmitting via the at least the second processing unit a glitch confirmation signal.
Claims20
A method comprising:
- detecting, by a circuit included in a glitch detector coupled via a connection matrix to a first processing unit of a plurality of processing units, an indication of a glitch attack on a memory system;
- notifying, via the connection matrix, at least a second processing unit of the plurality of processing units of the detected indication of the glitch attack;
- subsequent to notifying at least the second processing unit, transmitting, via at least the second processing unit, a glitch confirmation signal;
- and
- subsequent to detecting the indication of the glitch attack, performing at least one glitch resistance operation that increases a resistance of the memory system to a subsequent glitch attack.
An apparatus, comprising:
- a plurality of processing units;
- a plurality of glitch detectors including circuits configured to detect an indication of a glitch associated with a glitch attack;
- a connection matrix to couple each of the plurality of glitch detectors to at least two of the plurality of processing units;
- and
- a memory controller configured to perform, subsequent to detection of the indication of the glitch associated with the glitch attack, at least one glitch resistance operation that increases a resistance of the apparatus to a subsequent glitch attack.
An apparatus comprising:
- a memory controller;
- a plurality of processing units coupled to the memory controller;
- a plurality of glitch detectors including circuits configured to detect an indication of a glitch associated with a glitch attack;
- a connection matrix to couple each of the plurality of glitch detectors to at least two of the plurality of processing units;
- and
- alarm circuitry coupled to the plurality of processing units configured to:
- receive from at least one processing unit of the plurality of processing units signaling indicative of the detected glitch;
- and
- trigger a glitch alarm, transmit signaling to cause performance of a glitch mitigation operation, or both;
- and
- wherein the memory controller is configured to perform, subsequent to detection of the indication of the glitch associated with the glitch attack, at least one glitch resistance operation that increases a resistance of the apparatus to a subsequent glitch attack.
Dependencies are inferred from the claim text.