Inrush current management in a memory array
AssigneeArm Limited
InventorsAndy Wangkun Chen, Yew Keong Chong
Life of this patent
Estimating the term…
Abstract
Inrush current in a memory such as SRAM cache may be managed by using one or more integrated delay elements such as inverters, RC delay lines, and the like to significantly slow down power down signal propagation between memory instances in a memory array. The delay in some examples may be between memory instances, while in other examples the delay is also introduced between bitcell arrays within a memory instance. By staggering the power up times of interconnected or chained memory instances, inrush current when powering the memory instances on or resuming from an inactive state may be reduced.
Claims20
A method of controlling application of a power signal to a plurality of memory instances formed in a device, each memory instance comprising peripheral circuitry and one or more bitcell arrays, the method comprising:
- receiving a power down signal at a bitcell array power input terminal of a first memory instance of the plurality of memory instances, the power down signal operable to power up or down one or more bitcell arrays in the first memory instance;
- providing a delayed bitcell array power ready signal at a first output terminal of the first memory instance, and providing a control circuitry power ready signal at a second output terminal of the first memory instance;
- and
- receiving the delayed bitcell array power ready signal at a bitcell array power input terminal of a second memory instance of the plurality of memory instances and receiving the control circuitry power ready signal at a retention power input terminal of the second memory instance, wherein the control circuitry power ready signal received at the retention power input terminal of the second memory instance controls application of power to peripheral circuitry of the second memory instance.
An apparatus, comprising:
- a first memory instance comprising one or more first bitcell arrays, a first power input terminal to receive a power down signal, a first output terminal to provide a delayed bitcell array power ready signal, and a second output terminal to provide a control circuitry power ready signal;
- and
- a second memory instance comprising one or more second bitcell arrays, a second power input terminal to receive the delayed bitcell array power ready signal, and a retention power input terminal to receive the control circuitry power ready signal, the second memory instance comprising circuitry such that the control circuitry power ready signal received at the retention power input terminal of the second memory instance controls application of power to peripheral circuitry of the second memory instance.
An article comprising:
- a non-transitory computer-readable medium to store computer-readable code for fabrication of a memory device comprising:
- a first memory instance to be formed in a circuit device, the first memory instance to comprise one or more first bitcell arrays, a first power input terminal to receive a power down signal, a first output terminal to provide a delayed bitcell array power ready signal, and a second output terminal to provide a control circuitry power ready signal;
- and
- a second memory instance to be formed in the circuit device, the second memory instance to comprise one or more second bitcell arrays, a second power input terminal to receive the delayed bitcell array power ready signal, a retention power input terminal to receive the control circuitry power ready signal, and circuitry to apply the control circuitry power ready signal received at the retention power input terminal of the second memory instance to control application of power to peripheral circuitry of the second memory instance.
Dependencies are inferred from the claim text.