Disaggregation of processing pipeline

A processing system, comprising:

• a network interface controller (NIC), for connection to a packet communication network;
• a first computational accelerator;
• a first memory;
• and
• a central processing unit (CPU), which is to receive a definition of a video processing pipeline comprising multiple sequential processing stages for processing an input video stream having a predefined video frame rate, to partition the video processing pipeline into a plurality of partitions to enable completion of all processing stages within a video frame duration that is determined by the predefined video frame rate, each partition comprising one or more successive stages of the video processing pipeline, including at least a first partition and a second partition following the first partition in the video processing pipeline, to instruct the first computational accelerator to execute the first partition of the video processing pipeline, whereby the first computational accelerator writes output data from a final stage of the first partition for a first video frame to an output buffer in the first memory, to instruct the NIC to copy the output data over the packet communication network to an input buffer in a second memory for execution of the second partition of the video processing pipeline on a second computational accelerator using the copied output data in the second memory as input data to a first stage of the second partition, and to cause the first computational accelerator to process the first partition of the video processing pipeline for a next video frame while the second computational accelerator processes the copied output data from the first video frame, thereby enabling real-time processing of consecutive video frames at the predefined video frame rate.

A computer program product, comprising a tangible, non- transitory computer-readable medium in which program instructions are stored, which instructions, when read by a computer, cause the computer to receive a definition of a video processing pipeline comprising multiple sequential processing stages for processing an input video stream having a predefined video frame rate, to partition the video processing pipeline into a plurality of partitions to enable completion of all processing stages within a video frame duration that is determined by the predefined video frame rate, each partition comprising one or more successive stages of the video processing pipeline, including at least a first partition and a second partition following the first partition in the video processing pipeline, to instruct a first computational accelerator to execute the first partition of the video processing pipeline, whereby the first computational accelerator writes output data from a final stage of the first partition for a first video frame to an output buffer in a first memory, to instruct a NIC to copy the output data over a packet communication network to an input buffer in a second memory for execution of the second partition of the video processing pipeline on a second computational accelerator using the copied output data in the second memory as input data to a first stage of the second partition, and to cause the first computational accelerator to process the first partition of the video processing pipeline for a next video frame while the second computational accelerator processes the copied output data from the first video frame, thereby enabling real-time processing of consecutive video frames at the predefined video frame rate.