Vector reduction processor

A method for performing vector reduction operations for a plurality of staggered input vectors at a plurality of cycles by a vector reduction circuit, the method comprising:

• receiving a first request to perform a first vector reduction operation on a first staggered input vector and a second request to perform a second vector reduction operation on a second staggered input vector, wherein the first vector reduction operation is different than the second vector reduction operation;
• at a given cycle:
• receiving, by a first cell of a plurality of cells of the vector reduction circuit, a first input element from a first plurality of input elements included in the first staggered input vector;
• receiving, by a second cell of the plurality of cells, a second input element from a second plurality of input elements included in the second staggered input vector, wherein the second staggered input vector is different than the first staggered input vector;
• performing the first vector reduction operation on the first staggered input vector while performing the second vector reduction operation on the second staggered input vector comprising:
• performing, by the first cell, a first vector reduction operation using the first input element of the first staggered input vector to generate a respective output element while performing, by the second cell, a second vector reduction operation using the second input element of the second staggered input vector to generate a respective output element;
• and
• providing, by the first cell and the second cell, the respective output element to a respective next cell of the plurality of cells or an output circuit.