Method and apparatus for efficient access to multidimensional data structures and/or other large data blocks

A method performed in a parallel processing unit comprising a plurality of multiprocessors, the method comprising:

• receiving by a memory access hardware circuit coupled to a multicore processor of the plurality of multicore processors, from the coupled multicore processor, a memory access request for a block of data, wherein each multicore processor includes a respectively different shared memory, wherein the memory access hardware circuit is one of a plurality of memory access circuitry each coupled to one of the multicore processors;
• and
• in response to the memory access request, accessing the block of data at a source memory location in the respectively different shared memory of the coupled multicore processor or the external memory, and asynchronously transferring by the memory access hardware circuit, the block of data from the source memory location to a destination memory location in the respectively different shared memory of the coupled multicore processor and an external memory,
• wherein the asynchronous transfer is from a location in the external memory to another location in the external memory, or from a location in the respectively different shared memory of the coupled multicore processor to another location in the respectively different shared memory of the coupled multicore processor.

A method performed in a parallel processing unit comprising a plurality of multiprocessors, the method comprising:

• receiving by a memory access hardware circuit coupled to a multicore processor of the plurality of multicore processors, from the coupled multicore processor, a memory access request for a block of data, wherein each multicore processor includes a respectively different non-cached shared memory, wherein the memory access hardware circuit is one of a plurality of memory access circuitry each coupled to one of the multicore processors;
• and
• in response to the memory access request, accessing the block of data at a source memory location in the respectively different non-cached shared memory of the coupled multicore processor or the external memory, and asynchronously transferring by the memory access hardware circuit, the block of data from the source memory location to a destination memory location in the respectively different non-cached shared memory of the coupled multicore processor and an external memory, wherein
• the asynchronous transfer is from a location in the external memory to another location in the external memory, or
• the asynchronous transfer is from a location in the respectively different shared memory of the coupled multicore processor to another location in the respectively different shared memory of the coupled multicore processor.

A memory access hardware circuit comprising:

• an interface to an external memory;
• a memory input/output interface to receive memory access requests from a multicore processor;
• at least one memory interface to a respectively different shared memory at each of one or more other multicore processors and the multicore processor, wherein the respectively different shared memory is a non-cached shared memory;
• and
• a processing pipeline configured to:
• receive, from the multicore processor, a memory access request for a block of data;
• and
• in response to the memory access request, access the block of data at a source memory location in the respectively different shared memory of the coupled multicore processor or the external memory, and asynchronously transfer the block of data from the source memory location to a destination memory location in the respectively different shared memory of the coupled multicore processor and the external memory, wherein
• the asynchronous transfer is from a location in the external memory to another location in the external memory, or
• the asynchronous transfer is from a location in the respectively different shared memory of the coupled multicore processor to another location in the respectively different shared memory of the coupled multicore processor.

A parallel processor comprising:

• an interface to an external memory;
• a plurality of multicore processors, each multicore processor having a respectively different shared memory, wherein the respectively different shared memory is a non-cached shared memory;
• and
• a plurality of memory access hardware circuits, each memory access hardware circuit being coupled to a multicore processor of the plurality of multicore processors and being configured to:
• receive, from the coupled multicore processor, a memory access request for a block of data;
• and
• in response to the memory access request, access the block of data at a source memory location in the respectively different shared memory of the coupled multicore processor or the external memory, and asynchronously transfer the block of data from the source memory location to a destination memory location in the respectively different shared memory of the coupled multicore processor or the external memory, wherein
• the asynchronous transfer is from a location in the external memory to another location in the external memory, or
• the asynchronous transfer is from a location in the respectively different shared memory of the coupled multicore processor to another location in the respectively different shared memory of the coupled multicore processor.