High performance processor with improved microprogram execution triggered with a single issued execution trigger instruction
AssigneeUbitium GmbH
InventorMartin Vorbach
Life of this patent
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Abstract
Implementations relate to a data processor that includes a data processing unit having a plurality of processing elements and a cache hierarchy including a plurality of levels of data caches. The data caches include a first level data cache connected to a second level data cache, and a main memory connected to the highest level cache of the cache hierarchy. At least one of the first level data cache or second level data cache is divided into a plurality of cache segments, and during operation of the data processor, at least some of the plurality of cache segments are excluded from cache operation. Each of the excluded cache segments is dedicated to an associated processing element as tightly coupled local access memory.
Claims20
A data processor implementing an instruction set architecture, the data processor comprising:
- a plurality of processing elements;
- a memory arrangement;
- loading circuitry;
- and
- an instruction issuer;
- wherein, for each respective processing element of at least some of the processing elements:
- the data processor is adapted for a part of the memory arrangement to be connected, at least temporarily, exclusively to the respective processing element;
- the loading circuitry is adapted to initiate loading of a microprogram, which is formed of a sequence of codes that correspond to respective operations, from a memory hierarchy into the part of the memory arrangement that is connected, at least temporarily, exclusively to the respective processing element;
- the respective processing element is adapted to respond to a single instruction received from the instruction issuer by executing an entirety of the microprogram using the connection of the respective processing element to the part of the memory arrangement that is connected, at least temporarily, to the respective processing element;
- and
- the executing causes the respective processing element to produce a result data output by processing a received operand data.
Dependencies are inferred from the claim text.