DRAM row copy

A method for using a system comprising an array of dynamic random access memory (DRAM), configured with at least one bank of memory, comprising a dual wordline activation (DWLA) module, the method comprising:

• receiving an indication that a data is to be copied from a first memory row to a second memory row via the DWLA module, wherein upon receiving the indication:
• activating the first memory row in a first section of a first bank of the at least one bank of memory of the DRAM;
• and
• activating the second memory row of one of the first section of the at least one bank of memory or a second section of the at least one bank of memory simultaneously;
• wherein:
• the first memory row and the second memory row of the at least one bank of memory are activated concurrently during a concurrent time interval such that via a digital circuit, (i) the first memory row is activated (ii) a plurality of bitlines associated with first memory row and the second memory row is activated and (iii) the second row is activated while the first row remains activated;
• reading the first memory row and
• copying data from the first memory row into the second memory row via a plurality of sense amplifiers coupled to a plurality of bitlines serving memories from the first memory row and the second memory row, the plurality of sense amplifiers commonly serving the first memory row and the second memory row or separately serving the first memory row and the second memory row and mutually coupled to an input/output bus of the at least one bank of memory.

A non-transitory computer readable medium configured to store instructions, executable by one or more processing modules for causing a DRAM system, having at least one bank of DRAM memories, each bank comprising an array of DRAM devices, to perform the following:

• identify memory locations from which to copy data from a first memory row to a second memory row in connection with activating the first memory row in a first section of a first bank of memory of the DRAM system and activating the second memory row of one of the first section of the at least one bank or a second section of the at least one bank of memory simultaneously;
• wherein:
• the first memory row and the second memory row of the at least one bank of memory are activated concurrently during a concurrent time interval such that via a digital circuit,
• the first memory row is activated
• a plurality of bitlines associated with first memory row and the second memory row is activated and the second row is activated while the first row remains activated;
• and
• copy of data from the first memory row, served by a first array of sense amplifiers, to the second memory row, served by the first array of sense amplifiers or served by a second array of sense amplifiers coupled, via an input/output bus, to the first array of sense amplifiers.