Semiconductor test apparatus using FPGA and memory control method for semiconductor test

A memory control method for a semiconductor test, performed by a semiconductor test apparatus, which includes a failure memory (FM) block, a buffer memory (BM) block, and a field programmable gate array (FPGA), the memory control method comprising:

• storing, by the FM block, failure data, which is generated from a result of testing a semiconductor device;
• copying the failure data to, and storing the failure data in, the BM block;
• and
• performing, by the FPGA, a first control operation for controlling the FM block and a second control operation for controlling the BM block,
• wherein the FPGA has a Ping Pong PHY IP configuration.

A semiconductor test apparatus comprising:

• a failure memory (FM) block configured to store failure data, which is generated from a result of testing a semiconductor device;
• a buffer memory (BM) block to/in which the failure data stored in the FM block is configured to be copied/stored;
• a field programmable gate array (FPGA) configured to perform a first control operation to control the FM block and a second control operation to control the BM block;
• and
• a printed circuit board (PCB) on which the FPGA, the FM block, and the BM block are mounted, wherein
• each of the FM and BM blocks includes first and second memory groups, and
• each of the first and second memory groups includes main and spare memories, which are mounted in top and bottom areas, respectively, of the PCB.