Semiconductor arrangement and method of manufacture
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsPei-Yu Wang, Sai-Hooi Yeong
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Abstract
A method for forming a semiconductor arrangement comprises forming a fin over a semiconductor layer. A gate structure is formed over a first portion of the fin. A second portion of the fin adjacent to the first portion of the fin and a portion of the semiconductor layer below the second portion of the fin are removed to define a recess. A stress-inducing material is formed in the recess. A first semiconductor material is formed in the recess over the stress-inducing material. The first semiconductor material is different than the stress-inducing material.
Claims20
A semiconductor arrangement, comprising:
- a fin over a semiconductor layer;
- a gate structure over a portion of the fin and over a portion of the semiconductor layer;
- a stress-inducing material adjacent the portion of the fin and the portion of the semiconductor layer;
- a first semiconductor material overlying the stress-inducing material such that the stress-inducing material is between the first semiconductor material and the semiconductor layer and spaces the first semiconductor material apart from the semiconductor layer, wherein:
- the first semiconductor material is different than the stress-inducing material, and
- the first semiconductor material contacts a sidewall of the fin;
- and
- an isolation structure, wherein an uppermost surface of the stress-inducing material is above an uppermost surface of the isolation structure.
A semiconductor arrangement, comprising:
- a fin over a semiconductor layer;
- a first gate structure over a first portion of the fin and over a first portion of the semiconductor layer;
- a second gate structure over a second portion of the fin and a second portion of the semiconductor layer;
- a stress-inducing material between the first portion of the fin and the second portion of the fin;
- a first semiconductor material overlying the stress-inducing material such that the stress-inducing material is between the first semiconductor material and a third portion of the semiconductor layer underlying the stress-inducing material so as to space the first semiconductor material apart from the third portion of the semiconductor layer;
- and
- an isolation structure contacting a sidewall of the first semiconductor material, wherein the stress-inducing material and the isolation structure each intersect a same plane extending parallel to a top surface of the semiconductor layer.
A semiconductor arrangement, comprising:
- a fin over a semiconductor layer;
- a gate structure over a portion of the fin and over a portion of the semiconductor layer;
- a stress-inducing material adjacent the portion of the fin and the portion of the semiconductor layer, wherein the stress-inducing material comprises a porous dielectric material configured to shrink upon application of heat;
- and
- a first semiconductor material overlying the stress-inducing material such that the stress-inducing material is between the first semiconductor material and the semiconductor layer so as to space the first semiconductor material apart from the semiconductor layer, wherein:
- the first semiconductor material is different than the stress-inducing material, and
- the first semiconductor material contacts a sidewall of the fin.
Dependencies are inferred from the claim text.