Controlling trap formation to improve memory window in one-time program devices

A memory device comprising a one-time program (OTP) memory cell, wherein the OTP memory cell comprises:

• a semiconductor substrate;
• a read gate dielectric layer overlying the semiconductor substrate;
• a read gate electrode overlying the read gate dielectric layer;
• an interfacial layer overlying the semiconductor substrate;
• a program gate dielectric layer overlying the interfacial layer;
• a program gate electrode overlying the program gate dielectric layer and having a first sidewall and a second sidewall on opposite sides of the program gate electrode;
• and
• a source/drain region in the semiconductor substrate, between and bordering the read and program gate electrodes;
• wherein the read and program gate dielectric layers share a common material, wherein the program gate dielectric layer is thinner than the read gate dielectric layer, wherein the read and program gate dielectric layers have individual top surfaces with plasma etch damage, wherein the individual top surface of the program gate dielectric layer at a single elevation over the interfacial layer has a greater amount of plasma etch damage than the individual top surface of the read gate dielectric layer, and wherein the program gate dielectric layer and the interfacial layer extend along the read and program sidewalls of the program gate electrode and arm continuous from the read sidewall to the program sidewall.

A one-time program (OTP) memory cell, comprising:

• a read transistor over a substrate, and comprising a read gate electrode and a read dielectric layer between the read gate electrode and the substrate;
• and
• a program transistor over the substrate and coupled in series with the program transistor, and comprising a program gate electrode and a program dielectric layer between the program gate electrode and the substrate,
• wherein a top surface of the program dielectric layer has a first portion and a second portion at a same elevation and underlying the program gate electrode,
• wherein the read dielectric layer has a first average surface roughness, and
• wherein the first and second portions of the top surface of the program dielectric layer at the same elevation have a second average surface roughness that is greater than the first average surface roughness of the read dielectric layer.