Printed circuit board for phased array antenna transceiver assembly, transceiver assembly and radar

A transceiver assembly, configured to be connected to one or more antenna units and comprising:

• a printed circuit board for a phased array antenna transceiver assembly, comprising:
• a microwave c ore board layer, operating in a first frequency band, wherein a chip carrying area is arranged on a side of the microwave core board layer, and the chip carrying area is configured to carry a chip;
• a digital core board layer, operating in a second frequency band and stacked on another side of the microwave core board layer away from the chip carrying area;
• wherein an interlayer connecting path is arranged on the microwave core board layer and the digital core board layer, and the interlayer connecting path is connected to the chip carrying area;
• and
• a heat dissipation member, embedded in the digital core board layer and connected to the chip carrying area;
• and
• at least one chip, disposed on the chip carrying area and corresponding to the chip carrying area in a one-to-one manner;
• wherein the interlayer connecting path is configured to connect the chip disposed on the chip carrying area.

A radar, comprising:

• several antenna units, configured to transmit and receive signals;
• and
• a transceiver assembly, connected to the several antenna units, and configured to receive or output the signals;
• wherein the transceiver assembly comprises:
• a printed circuit board for a phased array antenna transceiver assembly, comprising:
• a microwave core board layer, operating in a first frequency band, wherein a chip carrying area is arranged on a side of the microwave core board layer, and the chip carrying area is configured to carry a chip;
• a digital core board layer, operating in a second frequency band and stacked on another side of the microwave core board layer away from the chip carrying area;
• wherein an interlayer connecting path is arranged on the microwave core board layer and the digital core board layer, and the interlayer connecting path is connected to the chip carrying area;
• and
• a heat dissipation member, embedded in the digital core board layer and connected to the chip carrying area;
• and
• at least one chip, disposed on the chip carrying area and corresponding to the chip carrying area in a one-to-one manner;
• wherein the interlayer connecting path is configured to connect the chip disposed on the chip carrying area.