Device for CAN bus

A network comprising:

• a serial two-wire bus having a first line and a second line;
• and
• a plurality of devices, each device having its first terminal connected to the first line, its second terminal connected to the second line, its third terminal intended to be connected to a power supply potential, and its fourth terminal connected to a reference potential, wherein a first device of the plurality of devices comprises:
• a first diode having a first electrode connected to a third terminal of the first device;
• a first branch comprising a first PMOS transistor and a first resistor in series between a second electrode of the first diode and a first terminal of the first device, and a second resistor, a second NMOS transistor and a second diode in series between the first terminal and fourth terminal of the first device;
• a second branch comprising a third PMOS transistor and a third resistor in series between the second electrode of the first diode and a second terminal of the first device, and a fourth resistor, a fourth NMOS transistor and a third diode in series between the second terminal and the fourth terminal of the first device;
• and
• a control circuit configured, at each consecutive transmission of a dominant bit and of a recessive bit on the serial two-wire bus by the first device, to set the first PMOS, second NMOS, third PMOS, and fourth NMOS transistors at the ON state during a whole first time period starting with the recessive bit.

A vehicle comprising a network, wherein the network comprises:

• a serial two-wire bus having a first line and a second line;
• and
• a plurality of devices, each device having its first terminal connected to the first line, its second terminal connected to the second line, its third terminal intended to be connected to a power supply potential, and its fourth terminal connected to a reference potential, wherein a first device of the plurality of devices comprises:
• a first diode having a first electrode connected to a third terminal of the first device;
• a first branch comprising a first PMOS transistor and a first resistor in series between a second electrode of the first diode and a first terminal of the first device, and a second resistor, a second NMOS transistor and a second diode in series between the first terminal and a fourth terminal of the first device;
• a second branch comprising a third PMOS transistor and a third resistor in series between the second electrode of the first diode and a second terminal of the first device, and a fourth resistor, a fourth NMOS transistor and a third diode in series between the second terminal and the fourth terminal of the first device;
• and
• a control circuit configured, at each consecutive transmission of a dominant bit and of a recessive bit on the serial two-wire bus by the first device, to set the first PMOS, second NMOS, third PMOS, and fourth NMOS transistors at the ON state during a whole first time period starting with the recessive bit.