Dynamic configuration of spur cancellation

A first integrated circuit (IC), comprising:

• an interface circuit configured to receive a start time at which a second IC starts to operate at one or more first operating frequencies and receive an update time at which the second IC starts to operate at one or more second operating frequencies;
• and
• a spur parameter cancellation circuit configured to:
• perform spur cancellation on a signal of the first IC received at the start time to mitigate a first spur from the second IC operating at the one or more first operating frequencies, wherein, to perform the spur cancellation, the spur parameter cancellation circuit is configured to apply a first ratio between a local clock frequency of the first IC and a local clock frequency of the second IC at a first time;
• determine a change in the local clock frequency of the second IC at a second time closer to the update time than the first time;
• and
• update the spur cancellation on the signal of the first IC from the update time to mitigate a second spur from the second IC operating at the one or more second operating frequencies, wherein, to perform the updated spur cancellation, the spur parameter cancellation circuit is configured to apply a second ratio between the local clock frequency of the first IC and the changed local clock frequency of the second IC.

A system, comprising:

• an aggressor integrated circuit (IC) configured to:
• provide a start time at which the aggressor IC starts to operate at one or more first operating frequencies;
• a victim IC configured to:
• receive the start time;
• perform spur cancellation on a signal of the victim IC received at the start time to mitigate a first spur from the aggressor IC operating at the one or more first operating frequencies, wherein the spur cancellation is performed by applying a first ratio between a local clock frequency of the victim IC and a local clock frequency of the aggressor IC at a first time;
• receive an update time at which the aggressor IC starts to operate at one or more second operating frequencies;
• determine a change in the local clock frequency of the aggressor IC at a second time closer to the update time than the first time;
• and
• update the spur cancellation on the signal of the victim IC from the update time to mitigate a second spur from the aggressor IC operating at the one or more second operating frequencies, wherein the updated spur cancellation is performed by applying a second ratio between the local clock frequency of the victim IC and the changed local clock frequency of the aggressor IC.