Integrated circuit package with warpage control using cavity formed in laminated substrate below the integrated circuit die

An integrated circuit package, comprising:

• a support substrate formed by an insulating core layer, an electrically conductive layer over the insulating core layer and a solder mask layer over the electrically conductive layer, wherein the support substrate includes a die attach location and first connection pads;
• an integrated circuit chip having a front side with second connection pads and a back side, wherein the back side is mounted to an upper surface of the support substrate at the die attach location;
• wherein the upper surface of the support substrate includes a cavity located within the die attach location, said cavity extending under the back side of the integrated circuit chip, said cavity comprising an area where the solder mask layer and at least a portion of the electrically conductive layer are not present;
• and
• bonding wires between the first and second connection pads.