Erase operations in memory devices

A memory device, comprising:

• a memory cell array;
• and
• a peripheral circuit coupled to the memory cell array and configured to perform operations comprising:
• erasing, during an erase operation of a target block in the memory cell array, one or more memory cells in the target block;
• verifying, during the erase operation of the target block, whether the one or more memory cells are erased;
• and
• respectively reading, during the erase operation of the target block, each of one or more blocks in the memory cell array, wherein respectively reading each of the one or more blocks comprises:
• applying a first voltage to a first select gate line coupled to a first select gate transistor in the target block;
• and
• applying a second voltage to a second select gate line coupled to a second select gate transistor in one of the one or more blocks, wherein the first voltage is lower than the second voltage.

A memory system, comprising:

• a memory device, comprising:
• a memory cell array;
• and
• a peripheral circuit coupled to the memory cell array and configured to perform operations comprising:
• erasing, during an erase operation of a target block in the memory cell array, one or more memory cells in the target block;
• verifying, during the erase operation of the target block, whether the one or more memory cells are erased;
• and
• respectively reading, during the erase operation of the target block, each of one or more blocks in the memory cell array, wherein respectively reading each of the one or more blocks comprises:
• applying a first voltage to a first select gate line coupled to a first select gate transistor in the target block;
• and
• applying a second voltage to a second select gate line coupled to a second select gate transistor in one of the one or more blocks, wherein the first voltage is lower than the second voltage;
• and
• a controller coupled to the memory device and configured to send one or more signals to the memory device to initiate the operations.