Resistive random access memory based one-time-programmable memory devices
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsYu-Der Chih, Chung-Cheng Chou
Life of this patent
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Abstract
A memory device includes a first memory array including a plurality of first memory bits. Each of the plurality of first memory bits is configured as a one-time-programmable (OTP) memory bit. A second memory array includes a plurality of second memory bits, each of the plurality of second memory bits being configured as a multi-time-programmable (MTP) memory bit. A lock bit circuit operatively coupled to the first memory array and not the second memory array. The lock bit circuit is configured to generate a lock bit indicative of whether at least one of the plurality of first memory bits has been programmed.
Claims20
A memory device, comprising:
- a first memory array including a plurality of first memory bits, each of the plurality of first memory bits being configured as a one-time-programmable (OTP) memory bit;
- a second memory array including a plurality of second memory bits, each of the plurality of second memory bits being configured as a multi-time-programmable (MTP) memory bit;
- and
- a lock bit circuit operatively coupled to the first memory array;
- wherein the lock bit circuit is configured to generate a lock bit indicative of whether at least one of the plurality of first memory bits has been programmed.
A memory device, comprising:
- a first memory array including a plurality of first memory bits, each of the plurality of first memory bits comprising a first access transistor and a first resistor coupled in series, the first resistor having a first variable resistance;
- and
- a lock bit circuit operatively coupled to the first memory array;
- wherein the lock bit circuit is configured to generate a lock bit indicative of whether at least one of the plurality of first memory bits has been permanently programmed from a first resistance to a second resistance, the second resistance being lower than the first resistance.
A method for operating a memory device, comprising:
- providing a memory array including a plurality of resistive random access memory (RRAM) bits;
- permanently programming at least one of the plurality of RRAM bits based on changing a resistance of the at least one RRAM bit;
- comparing the resistance of the at least one RRAM bit with a reference resistance;
- and
- generating, based on the comparison, a lock bit indicating whether the at least one RRAM bit has been permanently programmed.
Dependencies are inferred from the claim text.