Dynamic rowhammer management with per-row hammer tracking

A system for per-row hammer tracking in a DRAM device, comprising:

• aggressor processing circuitry comprising:
• an activation command (ACT) detecting circuitry to monitor or detect a number of row activation commands directed to each row of a bank of the DRAM device;
• a next aggressor row circuitry to determine a next aggressor row based on the number of row activation commands;
• a next aggressor row buffer coupled to the next aggressor row circuitry storing a row to which the greatest number of row activation commands have been directed;
• a next aggressor row count buffer coupled to the next aggressor row buffer storing
• a number of activation commands directed to the row stored in the next aggressor row buffer;
• mitigation processing circuitry comprising:
• a current aggressor row buffer coupled to the next aggressor row buffer for storing a current aggressor row that is the row stored in the next aggressor row buffer;
• a current aggressor count buffer coupled to the next aggressor row count buffer and storing the number of activation commands stored in the next aggressor count buffer;
• refresh command detecting circuitry to detect a refresh command directed to the bank;
• victim lookup circuitry coupled to the current aggressor row buffer to identify one or more victim rows physically proximate to the current aggressor row and for populating a victim queue;
• victim queue circuitry coupled to the victim lookup circuitry and determining whether the victim queue is empty and configured to initiate refreshing a row in the victim queue based on detection of a refresh command directed to the bank and a determination the victim queue is not empty;
• and
• wherein the mitigation processing circuitry is further configured to update a current aggressor row with the next aggressor row based on detection by the refresh command detecting circuitry of a refresh command directed to the bank.

A dynamic random access memory (DRAM) device, comprising:

• at least one data storage array comprising a plurality of rows;
• refresh processing circuitry configured to direct refresh operations to the data storage array;
• row hammering processing circuitry, comprising aggressor processing circuitry and mitigation processing circuitry;
• wherein an activation command (ACT) detecting circuitry of the aggressor processing circuitry is configured to monitor or detect a number of row activation commands directed to each row of a bank of the DRAM device and a next aggressor row circuitry is configured to determine a next aggressor row based on the number of row activation commands;
• a next aggressor row buffer is coupled to the next aggressor row circuitry and stores a row to which the greatest number of row activation commands have been directed;
• a next aggressor row count buffer is coupled to the next aggressor row buffer storing a number of activation commands directed to the row stored in the next aggressor row buffer;
• wherein the mitigation processing circuitry comprises:
• a current aggressor row buffer storing the next aggressor row based on detection of a refresh command directed to the bank;
• a current aggressor count buffer coupled to the next aggressor row count buffer and storing the number of activation commands stored in the next aggressor count buffer;
• refresh command detecting circuitry to detect a refresh command directed to the bank;
• victim lookup circuitry coupled to the current aggressor row buffer to identify one or more victim rows physically proximate to the current aggressor row and for populating a victim queue;
• victim queue circuitry coupled to the victim lookup circuitry and determining whether the victim queue is empty and configured to initiate refreshing a row in the victim queue based on detection of a refresh command directed to the bank and a determination the victim queue is not empty;
• and
• wherein the aggressor processing circuitry is further configured to reset the next aggressor row count buffer, following the updating of the current aggressor row, the next aggressor row count buffer's count of the number of row activation commands directed to the next aggressor row.