Apparatuses and methods for providing command having on-the-fly (OTF) latency to memory
AssigneeSamsung Electronics Co., Ltd.
InventorYounghwa Kim
Life of this patent
Estimating the term…
Abstract
A memory device supporting OTF latency includes a plurality of signal pins connected to a plurality of signal lines; and a control logic circuit configured to receive an OTF command including a command latency (CDL) value indicating the OTF latency through command lines among the plurality of signal lines, and control an operation of the memory device to be performed based on the OTF latency and a time point at which the OTF command is applied.
Claims20
A memory device configured to receive an on-the-fly (OTF) latency, the memory device comprising:
- a plurality of signal pins connected to a plurality of signal lines;
- and
- a control logic circuit configured to, during performance of a first operation:
- receive an OTF command including a command latency (CDL) value indicating the OTF latency, from an external device, through command lines among the plurality of signal lines, and
- control a second operation, different from the first operation, of the memory device to be performed based on the OTF latency and a time point at which the OTF command is applied.
A memory device comprising:
- a plurality of signal pins connected to a plurality of signal lines;
- and
- a control logic circuit configured to:
- receive an OTF command including a command latency (CDL) value indicating an OTF latency, from an external device, through command lines among the plurality of signal lines when data lines of the plurality of signal lines toggle data corresponding to data bursts of the memory device during performance of a first operation, and
- control a second operation, different from the first operation, of the memory device to be performed based on the OTF latency of the OTF command and a time point at which the OTF command is applied.
An operating method of a memory device configured to receive an on-the-fly (OTF) latency, the method comprising:
- receiving an OTF command including a command latency (CDL) value indicating the OTF latency through a command address bus among a plurality of buses during performance of a first operation;
- and
- performing a second operation, different from the first operation, of the memory device based on the OTF latency and a time point at which the OTF command is applied,
- wherein the command address bus is configured to receive a plurality of command and address signals including the OTF command and an address related to the OTF command.
Dependencies are inferred from the claim text.