Semiconductor memory systems with on-die data buffering

A semiconductor memory chip package, comprising:

• a package substrate;
• a semiconductor base IC chip mounted on the package substrate and configured as a master chip;
• and
• multiple memory integrated circuit (IC) chips stacked vertically on the semiconductor base IC chip and configured as minion IC chips;
• wherein the semiconductor base IC chip further comprises
• a primary interface to couple to a memory controller, the primary interface to transfer first data between the semiconductor base IC chip and the memory controller at a first data rate, and
• a secondary interface to couple to the multiple memory IC chips by through-silicon vias, the secondary interface to transfer second data between the semiconductor base IC chip and the multiple memory IC chips at a second data rate, wherein the first data rate is a multiple of the second data rate;
• wherein memory operations between the memory controller and any of the multiple memory IC chips are retransmitted through the semiconductor base IC chip.

A semiconductor module, comprising:

• a module substrate;
• and
• multiple memory devices mounted on the module substrate, wherein ones of the multiple memory devices comprise:
• a package substrate disposed on the module substrate;
• a semiconductor base die mounted on the package substrate and configured as a master die, the semiconductor base die comprising a primary interface to couple to a memory controller, the primary interface to transfer first data between the semiconductor base die and the memory at a first data rate, the semiconductor base die including a secondary interface;
• multiple memory die stacked vertically on the semiconductor base die and configured as minion die, the multiple memory die coupled to the secondary interface of the semiconductor base die by through-silicon vias, the secondary interface to transfer second data between the semiconductor base die and the multiple memory die at a second data rate, wherein the first data rate is a multiple of the second data rate;
• and
• wherein memory operations between the memory controller and any of the multiple memory die are retransmitted through the semiconductor base die.