Memory device reducing i/o signal lines through i/o mapping connection and memory system including the same

A memory device connected to a memory controller comprising:

• a first memory chip configured to receive input/output signals from the memory controller through first input/output pads;
• a second memory chip having second input/output pads normally connected to the first input/output pads;
• a third memory chip having third input/output pads mapped to the first input/output pads or the second input/output pads;
• and
• a fourth memory chip having fourth input/output pads normally connected to the third input/output pads;
• the third memory chip being configured to receive input/output signals different from the input/output signals provided by the memory controller to the first memory chip through a mapping connection, and
• the third and fourth memory chips are configured to selectively ignore the input/output signals provided by the memory controller based on a control signal being received by the first memory chip, the second memory chip, the third memory chip, and the fourth memory chip.

A memory system comprising:

• a memory device including a package of a first memory chip configured to receive input/output signals through first input/output pads and a second memory chip having second input/output pads connected to the first input/output pads based on a mapping connection;
• and
• a memory controller configured to provide the input/output signals to the memory device,
• the second memory chip being configured to receive input/output signals different from the input/output signals provided by the memory controller to the first memory chip based on the mapping connection, and
• the first and second memory chips are configured to selectively ignore the input/output signals provided by the memory controller based on a control signal received by the first memory chip and the second memory chip.