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US 12,493,340 B2Granted
Power-on-reset signal isolation during lower power mode
AssigneeTexas Instruments Incorporated
InventorsVenkateswar Kowkutla, Chunhua Hu, Raghavendra Santhanagopal, Kazunobu Shin, Charles Gerlach, Rejitha Nair, Ritesh Sojitra, Sai Rajaraman, Anthony Seely, Siva Srinivas Kothamasu, Varun Singh, John Apostol
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Abstract
A circuit device is provided and includes a first power domain comprising a universal serial bus (USB) subsystem and/or a memory controller subsystem. The first power domain is configured to isolate the USB subsystem and/or the memory controller subsystem from a power-on-reset signal asserted during a low power mode.
Claims20
A circuit device comprising:
- a first power domain comprising:
- a universal serial bus (USB) subsystem configured to store a first value and enter a reset state in response to receiving a power-on-reset signal;
- a memory controller subsystem configured to store a second value and enter the reset state in response to receiving the power-on-reset signal;
- an intellectual property (IP) module configured to store a third value and enter the reset state in response to receiving the power-on-reset signal;
- a main controller configured to:
- cause the IP module to store the third value in memory external to the first power domain in preparation for a low power mode prior to activating the power-on-reset signal throughout the first power domain;
- activate the power-on-reset signal throughout the first power domain during the low power mode;
- and
- circuitry configured to isolate the USB subsystem and the memory controller subsystem, not the IP module, from the power-on-reset signal such that the third value, not the first and second values, is reset by the power-on-reset signal.
6 more elements
A method comprising:
- storing, in preparation for a low power mode, a first register value of an intellectual property (IP) module in memory external to the first power domain;
- activating a power-on-reset signal from a main controller of the first power domain during the low power mode to a plurality of subsystems of the first power domain, wherein the plurality of subsystems comprises the IP module and a memory controller subsystem coupled with the memory external to the first power domain;
- isolating the power-on-reset signal from the memory controller subsystem during the low power mode while providing the power-on-reset signal to the IP module during the lower power mode to reset the first register value in the IP module.
A method comprising:
- storing, in preparation for a low power mode, a first register value of an intellectual property (IP) module in memory external to the first power domain;
- activating a power-on-reset signal from a main controller of the first power domain during the low power mode to a plurality of subsystems of the first power domain, wherein the plurality of subsystems comprises the IP module and a USB subsystem comprising a clock input and a data input and having a linked connection with an external USB device;
- isolating the power-on-reset signal from the USB subsystem during the low power mode while providing the power-on-reset signal to the IP module during the lower power mode to reset the first register value in the IP module.
Dependencies are inferred from the claim text.