Test pattern reset control circuit

An integrated circuit comprising:

• a scan reset pad configured to receive a reset signal external to the integrated circuit;
• a plurality of circuit blocks comprising a set of scan flip-flops configured to be simultaneously reset by the reset signal;
• a plurality of writable non-scan test data registers comprising register outputs configured to assert or de-assert the reset signal;
• and
• a plurality of reset enable circuits coupled to the plurality of circuit blocks in a one-to-one ratio, each of the plurality of reset enable circuits comprising
• an input coupled to the scan reset pad,
• a selector input coupled to the register outputs, and
• an output coupled to the corresponding circuit block.

A method of testing an integrated circuit comprising a plurality of circuit blocks, the method comprising:

• shifting a first test pattern into a plurality of sets of scan flip-flops of the integrated circuit, each set of scan flip-flops being comprised within a corresponding circuit block of the plurality of circuit blocks in a one-to-one ratio;
• storing a first reset pattern in a plurality of writable non-scan test data registers of the integrated circuit;
• asserting a scan reset signal at a scan reset pad of the integrated circuit to test for reset faults;
• deasserting the scan reset signal to a first subset of circuit blocks of the plurality of circuit blocks and asserting the scan reset signal to the remaining circuit blocks not in the first subset at outputs of the writable non-scan test data registers using the first reset pattern;
• launching the first test pattern while the scan reset signal is deasserted to the first subset of circuit blocks and asserted to the remaining circuit blocks not in the first subset;
• and
• capturing results of the first test pattern.