Vertically stacked cascode bipolar junction transistor (BJT) pair sensor
AssigneeInternational Business Machines Corporation
InventorsAlexander Reznicek, Bahman Hekmatshoartabari
Life of this patent
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Abstract
A sensor device includes a vertically stacked cascode bipolar junction transistor pair, and a first trench having a first sidewall, wherein a portion of the first sidewall is provided by the first sensing surface, wherein a bipolar junction transistor and a dual-base bipolar junction transistor of the cascode bipolar junction transistor pair are stacked vertically along the first trench.
Claims20
A sensor device comprising:
- a vertically stacked cascode bipolar junction transistor pair comprising:
- a resistor;
- an NPN bipolar junction transistor connected to the resistor;
- and
- a dual-base NPN bipolar junction transistor comprising a sensing base and a first sensing surface connected to the sensing base;
- and
- a first trench having a first sidewall, wherein a portion of the first sidewall is provided by the first sensing surface,
- wherein the NPN bipolar junction transistor and the dual-base NPN bipolar junction transistor are stacked vertically along the first trench.
A sensor device comprising:
- a vertically stacked cascode bipolar junction transistor pair comprising:
- a dual-base PNP bipolar junction transistor comprising a sensing base and a first sensing surface connected to the sensing base;
- a PNP bipolar junction transistor connected to the dual-base PNP bipolar junction transistor;
- and
- a resistor;
- and
- a first trench having a first sidewall, wherein a portion of the first sidewall is provided by the first sensing surface,
- wherein the PNP bipolar junction transistor and the dual-base PNP bipolar junction transistor are stacked vertically along the first trench.
A method of manufacturing a sensor device comprising a vertically stacked cascode bipolar junction transistor pair, the method comprising:
- providing a stack including a substrate, an isolation layer, an emitter layer, a first base layer, a collector-emitter layer, a second base layer, a collector layer, and a resistor layer;
- patterning the stack to form a first fin and a second fin;
- sequentially forming an oxide liner, a bottom spacer material, a first sacrificial material, a first spacer layer, a second sacrificial material, a third spacer layer, and a silicon oxide layer;
- forming a first sample trench between the first fin and the second fin;
- forming first cavities by removing the first sacrificial material and the second sacrificial material;
- forming a plurality of extrinsic bases in the first cavities, the plurality of extrinsic bases including an upper extrinsic base and a lower extrinsic base;
- forming vertical cavities in the plurality of extrinsic bases;
- forming vertical spacers in the vertical cavities, the vertical spacers including an upper vertical spacer and a lower vertical spacer;
- forming a hanging spacer, which protects the upper extrinsic base and the upper vertical spacer;
- and
- replacing the lower vertical spacer with a metal sensing surface, wherein a portion of a sidewall of the first sample trench is provided by the metal sensing surface,
- wherein the first sample trench extends through the sensor device.
Dependencies are inferred from the claim text.