US 12,490,455 B2Granted

Semiconductor device

AssigneeSamsung Electronics Co., Ltd.

InventorsDeok Han Bae, Myung Yoon Um, Yu Ri Lee, Sun Me Lim, Jun Su Jeon

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Abstract

A semiconductor device includes an isolation structure having first and second sidewalls opposite each other, a first fin-shaped pattern in contact with the first sidewall and extending in the second direction, a second fin-shaped pattern in contact with the second sidewall and extending in the second direction, a first gate electrode on the first fin-shaped pattern, a first source/drain contact on the first and second fin-shaped patterns and extending between the first gate electrode and the element isolation structure, and a wiring structure on and connected to the first source/drain contact, wherein the first source/drain contact includes a lower contact intersecting the first and second fin-shaped patterns, an upper contact protruding from the lower contact, and a dummy contact, the wiring structure being in contact with the upper contact and not with the dummy contact.

Claims20

Dependent claims

A semiconductor device, comprising:

an element isolation structure having a first sidewall and a second sidewall extending in a first direction, the first sidewall being opposite to the second sidewall in a second direction;
a first fin-shaped pattern in contact with the first sidewall of the element isolation structure, the first fin-shaped pattern extending in the second direction;
a second fin-shaped pattern in contact with the first sidewall of the element isolation structure, the second fin-shaped pattern extending in the second direction and being spaced apart from the first fin-shaped pattern in the first direction;
a first gate electrode extending in the first direction and disposed on the first fin-shaped pattern;
a first source/drain contact disposed on the first fin-shaped pattern and the second fin-shaped pattern, the first source/drain contact extending in the first direction and disposed between the first gate electrode and the element isolation structure;
and
a wiring structure connected to the first source/drain contact and disposed on the first source/drain contact,
wherein the first source/drain contact includes a first lower contact region that is disposed on the first fin-shaped pattern and the second fin-shaped pattern, a first upper contact region that is disposed one the first lower contact region, and a first dummy contact region, and
wherein the wiring structure contacts an upper surface of the first upper contact region and is spaced apart from an upper surface of the first dummy contact region.

6 more elements

A semiconductor device, comprising:

a first fin-shaped pattern extending in a first direction;
a second fin-shaped pattern extending in the first direction and spaced apart from the first fin-shaped pattern in a second direction;
a third fin-shaped pattern extending in the first direction;
a fourth fin-shaped pattern extending in the first direction and spaced apart from the third fin-shaped pattern in the second direction;
an element isolation structure extending in the second direction and in contact with the first fin-shaped pattern and the second fin-shaped pattern;
a first gate electrode extending in the second direction and disposed on the first fin-shaped pattern;
a second gate electrode extending in the second direction and disposed on the third fin-shaped pattern;
a third gate electrode extending in the second direction and disposed on the fourth fin-shaped pattern;
a first source/drain contact disposed on the first fin-shaped pattern and the second fin-shaped pattern and disposed between the first gate electrode and the element isolation structure, the first source/drain contact extending in the second direction;
a second source/drain contact disposed on the third fin-shaped pattern and the fourth fin-shaped pattern, disposed between the second gate electrode and the element isolation structure, and disposed between the third gate electrode and the element isolation structure, the second source/drain contact extending in the second direction;
and
a wiring structure disposed on the first source/drain contact and the second source/drain contact, the wiring structure being connected to the first source/drain contact and the second source/drain contact,
wherein:
the first source/drain contact includes a first lower contact region disposed on the first fin-shaped pattern and the second fin-shaped pattern, and a first upper contact region disposed on the first lower contact region,
the second source/drain contact includes a second lower contact region disposed on the third fin-shaped pattern and the fourth fin-shaped pattern, and a second upper contact region disposed on the second lower contact region,
the wiring structure includes a via plug in contact with the first upper contact region and the second upper contact region,
a bottom surface of the via plug has a first width,
a width of an upper surface of the first upper contact region is greater than or equal to 1.5 times the first width, and
a width of an upper surface of the second upper contact region is less than or equal to 1.2 times the first width.

16 more elements

A semiconductor device, comprising:

a first fin-shaped pattern extending in a first direction;
a second fin-shaped pattern spaced apart from the first fin-shaped pattern in a second direction and extending in the first direction;
a third fin-shaped pattern spaced apart from the first fin-shaped pattern in the first direction and extending in the first direction;
a fourth fin-shaped pattern spaced apart from the second fin-shaped pattern in the first direction and extending in the first direction;
a first source/drain contact disposed on the first fin-shaped pattern and the second fin-shaped pattern, and extending in the second direction;
a second source/drain contact disposed on the third fin-shaped pattern, and the fourth fin-shaped pattern and extending in the second direction;
an element isolation structure disposed between the first fin-shaped pattern and the third fin-shaped pattern and disposed between the second fin-shaped pattern and the fourth fin-shaped pattern;
and
a wiring structure disposed on the first source/drain contact and the second source/drain contact, and connected to the first source/drain contact and the second source/drain contact,
wherein:
the first source/drain contact includes a first lower contact region disposed on the first fin-shaped pattern and the second fin-shaped pattern, a first upper contact region disposed on the first lower contact region, and a first dummy contact region,
the second source/drain contact includes a second lower contact region disposed on the third fin-shaped pattern and the fourth fin-shaped pattern, and a second upper contact region disposed on the second lower contact region, and
the wiring structure is in contact with an upper surface of the first upper contact region and an upper surface of the second upper contact region, and is not in contact with an upper surface of the first dummy contact region.

10 more elements

Dependencies are inferred from the claim text.

Facts

Application: 17/989,944Filed 18 Nov 2022
Priority: KR 10-2022-00540362 May 2022
Published: US 2023/0352591 A12 Nov 2023
Granted: 2 Dec 2025
Term ends: Not estimatedThe source records don’t support an estimate.

Classification22 codes

H10D 30/6211
Fin field-effect transistors [FinFET]: having fin-shaped semiconductor bodies integral with the bulk semiconductor substrates
H10D 84/0188
The components including complementary IGFETs, e.g. CMOS devices: manufacturing their isolation regions
H10D 30/019
Manufacture or treatment: of FETs having stacked nanowire, nanosheet or nanoribbon channels
H10D 30/6219
Fin field-effect transistors [FinFET]: characterised by the source or drain electrodes