Integrated assemblies having transistors configured for high-voltage applications, and methods of forming integrated assemblies

An integrated assembly, comprising:

• a first gate coupled to a voltage and operatively adjacent a channel region;
• a first source/drain region on a first side of the channel region along a first direction, and a second source/drain region on a second side of the channel region in the first direction;
• a second gate over the first side and laterally spaced apart from a first sidewall of the first gate in the first direction;
• and
• a third gate over the second side and laterally spaced apart from a second sidewall of the first gate in the first direction, at least one of the second and third gate coupled to a voltage different from the voltage of the first gate.

An integrated assembly, comprising:

• a first gate over a first gate dielectric and operatively adjacent a channel region;
• a first source/drain region on a first side of the channel region along a first direction, and a second source/drain region on a second side of the channel region in the first direction;
• a second gate over the first side, laterally spaced apart from a first sidewall of the first gate in the first direction and against a second gate dielectric that is a different structure from the first gate dielectric;
• and
• a third gate over the second side, laterally spaced apart from a second sidewall of the first gate in the first direction and against a third gate dielectric that is a different structure from the first gate dielectric.

An integrated assembly, comprising:

• a first gate operatively adjacent a channel region;
• a first source/drain region on a first side of the channel region, and a second source/drain region on a second side of the channel region, with the second side being in opposing relation to the first side;
• the first source/drain region being spaced from the channel region by an intervening region;
• the first and second source/drain regions being gatedly coupled to one another through the channel region;
• a second gate adjacent a segment of the intervening region and spaced from the first gate by an insulative region;
• a lightly-doped region extending across the intervening region and being under at least a portion of the first source/drain region;
• and
• wherein the intervening region is a first intervening region, and further comprising:
• a second intervening region between the second source/drain region and the channel region;
• and
• a third gate adjacent a segment of the second intervening region;
• and
• wherein the first gate is coupled with driver circuitry configured to selectively provide voltage to the first gate to selectively induce an electric field within the channel region and thereby selectively transition the channel region between a first operational mode that couples the first and second source/drain regions with one another and a second operational mode that does not couple the first and second source/drain regions with one another;
• and wherein the second and third gates are also coupled with the driver circuitry.