Manufacturing method of a semiconductor device with junction field effect transistor

A manufacturing method of a semiconductor device, comprising:

• forming a base region in a substrate;
• forming a first sacrificial layer on the substrate, wherein the first sacrificial layer covers the base region;
• performing a photolithography process and a first etching process to pattern the first sacrificial layer, thereby forming a first distance between a vertical projection of an inner sidewall of the first sacrificial layer on the substrate and an inner side of the base region;
• forming a junction field effect transistor region in the substrate by using the first sacrificial layer as a mask;
• forming a second sacrificial layer on the substrate, wherein the second sacrificial layer covers the junction field effect transistor region;
• performing a second etching process to remove the first sacrificial layer;
• forming a well region in the substrate by using the second sacrificial layer as a mask, wherein the well region is adjacent to the base region, and the well region is in contact with a bottom portion of the base region;
• expanding the second sacrificial layer, thereby forming a second distance between a vertical projection of an outer sidewall of the second sacrificial layer on the substrate and an outer side of the junction field effect transistor region;
• forming a source region in the substrate by using the second sacrificial layer as a mask, wherein the well region is adjacent to the source region, and the well region is in contact with the bottom portion of the base region and a bottom portion of the source region;
• and
• removing the second sacrificial layer.

A manufacturing method of a semiconductor device, comprising:

• forming base region in a substrate;
• forming a protective layer on the substrate, wherein the protective layer covers the base region;
• forming a first sacrificial layer and a second sacrificial layer on the substrate, wherein the first sacrificial layer and the second sacrificial layer covers the protective layer;
• forming a source region, a well region, and a junction field effect transistor in the substrate, wherein:
• the source region, the well region, and the junction field effect transistor region are formed in sequence, the source region and the well region are formed by the first sacrificial layer that is patterned, and the junction field effect transistor region is formed by the second sacrificial layer;
• or
• the junction field effect transistor region, the well region, and the source region are formed in sequence, the junction field effect transistor region is formed by the first sacrificial layer that is patterned, and the well region and the source region are formed by the second sacrificial layer.