Discrete-time linear equalizer for discrete-time analog front-end

A method comprising:

• performing signal equalization of a modulated voltage signal by:
• sampling the modulated voltage signal by charging a first capacitor with the modulated voltage signal over a first time period;
• sampling the modulated voltage signal by charging a second capacitor with the modulated voltage signal over a second time period;
• sampling the modulated voltage signal by charging a third capacitor with the modulated voltage signal over a third time period;
• and
• coupling the second capacitor to an output, and the first capacitor and the third capacitor in a closed feedback loop with the second capacitor, over a fourth time period.

An apparatus comprising:

• a discrete-time linear equalizer circuit comprising:
• a double-sampling sample and hold circuitry including multiple double-sampling switched-capacitor circuits and an operational amplifier, the multiple double-sampling switched-capacitor circuits including at least a double-sampling switched-capacitor circuit of a pre-cursor tap, a double-sampling switched-capacitor circuit of a cursor tap, and a double-sampling switched-capacitor circuit of a post-cursor tap, respective ones of the multiple double-sampling switched-capacitor circuits including a first capacitor and a second capacitor;
• a clock-driven switch circuitry of the multiple double-sampling switched-capacitor circuits to:
• switchably couple the first capacitor of the double-sampling switched-capacitor circuit of the pre-cursor tap between a signal input and a non-inverting input of the operational amplifier to charge the first capacitor with a modulated signal over a first sampling time period;
• switchably couple the first capacitor of the double-sampling switched-capacitor circuit of the cursor tap between the signal input and the non-inverting input of the operational amplifier to charge the first capacitor with the modulated signal over a second sampling time period;
• switchably couple the first capacitor of the double-sampling switched-capacitor circuit of the post-cursor tap between the signal input and the non-inverting input of the operational amplifier to charge the first capacitor with the modulated signal over a third sampling time period;
• and
• switchably couple the first capacitor of the double-sampling switched-capacitor circuit of the cursor tap between an amplifier output of the operational amplifier and an inverting input of the operational amplifier, and the first capacitor of the double-sampling switched-capacitor circuit of the pre-cursor tap and the first capacitor of the double-sampling switched-capacitor circuit of the post-cursor tap in a closed feedback loop with the first capacitor of the double-sampling switched-capacitor circuit of the cursor tap, over a first hold time period.

An apparatus comprising:

• a discrete-time linear equalizer, the discrete-time linear equalizer comprising a set of N time-multiplexed circuit threads of N discrete-time linear equalizer circuits, respective Mth ones of the N discrete-time linear equalizer circuits to perform signal equalization in relation to an Mth symbol and respective subsequent (i*N+M)th symbols of a modulated signal for consecutive positive integers i, wherein N is a positive integer and M is a positive integer from 1 to N, the respective Mth ones of the N discrete-time linear equalizer circuits comprising:
• a double-sampling sample and hold circuitry including multiple double-sampling switched-capacitor circuits and an operational amplifier, the multiple double-sampling switched-capacitor circuits including at least a double-sampling switched-capacitor circuit of a pre-cursor tap, a double-sampling switched-capacitor circuit of a cursor tap, and a double-sampling switched-capacitor circuit of a post-cursor tap, the double-sampling switched-capacitor circuit of the pre-cursor tap including a first capacitor C−1x and a second capacitor C−1y, the double-sampling switched-capacitor circuit of the cursor tap including a first capacitor C0x and a second capacitor C0y, and the double-sampling switched-capacitor circuit of the post-cursor tap including at least a first capacitor C1x and a second capacitor C1y;
• a clock-driven switch circuitry, the clock-driven switch circuitry to switchably couple the first capacitor C−1x to a signal input to charge the first capacitor C−1x with a modulated signal over an (M−1)th sampling time period, the first capacitor C0x to the signal input to charge the first capacitor C0x with the modulated signal over an Mth sampling time period, and the first capacitor C1x to the signal input to charge the first capacitor C1x with the modulated signal over an (M+1)th sampling time period;
• the clock-driven switch circuitry to switchably couple the first capacitor C0x to an amplifier output of the operational amplifier, and in closed feedback loop with the first capacitor C−1x and the first capacitor C1x, over an Mth hold time period;
• the clock-driven switch circuitry to switchably couple the second capacitor C−1y to the signal input to charge the second capacitor C−1y with the modulated signal over an (M+N+1)th sampling time period, the second capacitor C0y to the signal input to charge the second capacitor C0y with the modulated signal over an (M+N)th sampling time period, and the second capacitor C1y to the signal input to charge the second capacitor C1y with the modulated signal over an (M+N+1)th sampling time period;
• and
• the clock-driven switch circuitry to switchably couple the second capacitor C0y to the amplifier output of the operational amplifier, and in a closed feedback loop with the second capacitor C−1y and the second capacitor C1y, over an (M+N)th hold time period.