Device for processing homomorphically encrypted data

A system comprising:

• a device for processing homomorphically encrypted data;
• a processor;
• and
• a memory communicatively coupled to the processor storing instructions that when executed by the processor causes the processor to:
• send, using the memory, a plurality of parallel input data points derived from homomorphically encrypted data to the device for processing by the device;
• and
• receive, using the memory, a plurality of parallel output data points produced by the device from processing the plurality of parallel input data points,
• wherein the device comprises:
• a plurality of inter-line butterfly array blocks, each inter-line butterfly array block comprising a plurality of inter-line modulus butterfly units, the memory further comprising instructions for directing the processor to perform, using each inter-line modulus butterfly unit, a modulus butterfly operation based on a computation pair of data points received corresponding to a pair of input data points at a same row of a matrix of input data points;
• a plurality of intra-line butterfly array blocks, each intra-line butterfly array block comprising a plurality of intra-line modulus butterfly units, the memory further comprising instructions for directing the processor to perform, using each inter-line modulus butterfly unit, a modulus butterfly operation based on a computation pair of data points received corresponding to a pair of input data points at a same column of the matrix of input data points;
• and
• a clock counter communicatively coupled to each inter-line butterfly array block of the plurality of inter-line butterfly array blocks and each intra-line butterfly array block of the plurality of intra-line butterfly array blocks, the memory further comprising instructions for directing the processor to output, using the clock counter, a counter signal for controlling said each inter-line butterfly array block and said each intra-line butterfly array block to operate with single cycle initiation interval, wherein
• the matrix of input data points comprises a plurality of columns of input data points, wherein a plurality of parallel input data points derived from the homomorphically encrypted data are arranged into the plurality of columns of input data points, and
• the plurality of inter-line butterfly array blocks and the plurality of intra-line butterfly array blocks are arranged in series to form a pipeline for processing the matrix of input data points.

A method of forming a device for processing homomorphically encrypted data, the method comprising:

• performing a modulus butterfly operation based on a computation pair of data points received corresponding to a pair of input data points at a same row of a matrix of input data points using each inter-line modulus butterfly unit of a plurality of inter-line butterfly array blocks, each inter-line butterfly array block comprising a plurality of the inter-line modulus butterfly units;
• performing a modulus butterfly operation based on a computation pair of data points received corresponding to a pair of input data points at a same column of the matrix of input data points using each intra-line modulus butterfly unit of a plurality of intra-line butterfly array blocks, each intra-line butterfly array block comprising the plurality of intra-line modulus butterfly units;
• and
• outputting a counter signal for controlling said each inter-line butterfly array block and said each intra-line butterfly array block to operate with single cycle initiation interval using a clock counter communicatively coupled to each inter-line butterfly array block of the plurality of inter-line butterfly array blocks and each intra-line butterfly array block of the plurality of intra-line butterfly array blocks, wherein
• the matrix of input data points comprises a plurality of columns of input data points, wherein a plurality of parallel input data points derived from the homomorphically encrypted data are arranged into the plurality of columns of input data points, and
• the plurality of inter-line butterfly array blocks and the plurality of intra-line butterfly array blocks are arranged in series to form a pipeline for processing the matrix of input data points.