Single clock delay step in multi-stage switched-capacitor delays

A programmable delay device comprising:

• an input sampling stage adapted to receive an input sampling clock at a frequency FS and an input RF signal, the input sampling stage including M sampling switched capacitor storage elements, the M sampling switched capacitor storage elements adapted to sequentially sample and hold a corresponding portion of the input RF signal, the thus sampled and held portions of the input RF signal being input sampled signals;
• a programmable delay stage including M programmable switched capacitor banks, each programmable switched capacitor bank including N delay switched capacitor storage elements, each delay switched capacitor storage element adapted to sample and hold a corresponding time interleaved portion of a corresponding input sampled signal, the thus sampled and held signals being delay sampled switched signals;
• a programmable enable delay circuit adapted to receive a desired fine delay value and the input sampling clock, the programmable enable delay circuit adapted to generate an enable output signal with a time delay based upon the desired fine delay value, an incremental fine delay value corresponding to 1/FS, the programmable enable delay circuit adapted to output the enable output signal and the input sampling clock as an output clock;
• an enable timing circuit adapted to receive a desired coarse delay value, the enable output signal, and the output clock, the enable timing circuit including a digital counter, the digital counter adapted to count to the desired coarse delay value, upon reaching the desired coarse delay value the enable timing circuit is adapted to output a corresponding output reconstruction clock, an incremental coarse delay value corresponding to M/FS;
• and
• an output reconstruction stage including M output reconstruction switches, each output reconstruction switch coupled to a corresponding delay output switch, each output reconstruction switch adapted to output a corresponding time interleaved delay sampled switched signal based upon the output reconstruction clock, the thus output time interleaved delay sampled switched signals being output reconstruction signals, the output reconstruction stage adapted to output the output reconstruction signals in a sequential manner thereby generating a reconstructed output RF signal.