Lock-up latch for dual-edge-triggered flip-flops
AssigneeQUALCOMM Incorporated
InventorsYimai Peng, Robert Joseph Vachon, Daniel Yingling, Keith Alan Bowman
Life of this patent
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Abstract
An apparatus, including: a first flip-flop including a scan input configured to receive a scan signal, a clock input configured to receive a first clock signal of a first clock domain; a latch including an input coupled to an output of the first flip-flop, a clock input configured to receive a control signal; and a second flip-flop including a scan input coupled to an output of the latch, a clock input configured to receive a second clock signal of a second clock domain, and an output configured to generate the scan signal, wherein at least one of the first or second flip-flop comprises a first dual-edge-triggered (DET) flip-flop.
Claims13
An apparatus, comprising:
- a first flip-flop including a scan input configured to receive a scan signal, a clock input configured to receive a first clock signal of a first clock domain;
- a latch including an input coupled to an output of the first flip-flop, a clock input configured to receive a control signal;
- and
- a second flip-flop including a scan input coupled to an output of the latch, a clock input configured to receive a second clock signal of a second clock domain, and an output configured to generate the scan signal,
- wherein one of the first or second flip-flop comprises a dual-edge-triggered (DET) flip-flop, and
- wherein the other of the first or second flip-flop comprises a single-edge-triggered (SET) flip-flop.
A method, comprising:
- operating a first flip-flop to propagate a scan signal from an input to an output based on a first clock signal of a first clock domain;
- operating a latch to propagate the scan input from an input to an output based on a control signal;
- and
- operating a second flip-flop to propagate the scan signal from an input to an output based on a second clock signal of a second clock domain, wherein one of the first or second flip-flop comprises a dual-edge-triggered (DET) flip-flop, and
- wherein the other of the first or second flip-flop comprises a single-edge-triggered (SET) flip-flop.
A wireless communication device, comprising:
- at least one antenna;
- a transceiver coupled to the at least one antenna;
- and
- one or more signal processing cores coupled to the transceiver, wherein the one or more signal processing cores comprise:
- a first flip-flop including a scan input configured to receive a scan signal, a clock input configured to receive a first clock signal of a first clock domain;
- a latch including an input coupled to an output of the first flip-flop, a clock input configured to receive a control signal;
- and
- a second flip-flop including a scan input coupled to an output of the latch, a clock input configured to receive a second clock signal of a second clock domain, and an output configured to generate the scan signal,
- wherein one of the first or second flip-flop comprises a dual-edge-triggered (DET) flip-flop, and
- wherein the other of the first or second flip-flop comprises a single-edge-triggered (SET) flip-flop.
Dependencies are inferred from the claim text.