Semiconductor chip and semiconductor package including bonding layers having alignment marks

A semiconductor package, comprising:

• a first semiconductor chip including a first substrate and a first bonding layer disposed on the first substrate, and having an upper surface provided by the first bonding layer;
• and
• a second semiconductor chip disposed on the upper surface of the first semiconductor chip, including a second substrate and a second bonding layer disposed below the second substrate, and having a lower surface provided by the second bonding layer and in contact with the upper surface of the first semiconductor chip,
• wherein the first bonding layer includes first external marks and a first external pad providing the upper surface, the first external marks and the first external pad electrically insulated from each other, and the first external marks include concentric portions that include a center portion and a ring portion surrounding the center portion with a gap between the center portion and the ring portion,
• wherein the second bonding layer includes second external marks and a second external pad providing the lower surface, the second external marks and the second external pad electrically insulated from each other, and the second external marks include concentric portions that include a center portion and a ring portion surrounding the center portion with a gap between the center portion and the ring portion, and
• wherein a difference between a width in a first horizontal direction of the first external marks and a width in the first horizontal direction of the first external pad is 20% or less and a difference between a width in the first horizontal direction of the second external marks and a width in the first horizontal direction of the second external pad is 20% or less.

A semiconductor package, comprising:

• a first semiconductor chip including a first substrate and a first bonding layer disposed on the first substrate, and having a flat upper surface provided by the first bonding layer;
• and
• a second semiconductor chip disposed on the upper surface of the first semiconductor chip, including a second substrate and a second bonding layer disposed below the second substrate, and having a lower surface provided by the second bonding layer and contacting the upper surface of the first semiconductor chip,
• wherein the first bonding layer includes a first alignment structure having first external marks providing the upper surface and including concentric portions having a first gap therebetween, and a first internal mark disposed in the first gap when viewed from a plan view, below the first external marks, and a first pad structure having a first external pad electrically insulated from the first external marks, and
• wherein the first alignment structure has a planar area larger than a planar area of the first external pad, when both are projected onto a plane parallel to the upper surface of the first semiconductor chip.