Systems and methods to avoid over programming at infrequent smart verify acquisition for high-performance 3D NAND

A method of programming a memory device, comprising the steps of:

• performing a smart verify operation to acquire an initial programming voltage;
• performing a program operation on a selected wordline starting with the initial programming voltage;
• performing a bitscan operation of a highest state being verified;
• based on a result of the bitscan operation, adjusting the initial programming voltage for programming of subsequent wordlines;
• and
• in response to the result of the bitscan operation failing, initiating a verify of a next data state in a next program loop of a plurality of program loops of the program operation.

A memory device, comprising:

• at least one memory block that includes a plurality of memory cells arranged in a plurality of word lines;
• control circuitry configured to program the memory cells of the at least one memory block in a plurality of program loops, the control circuitry being configured to:
• perform a smart verify operation to acquire an initial programming voltage;
• perform a program operation on a selected wordline starting with the initial programming voltage;
• perform a bitscan operation of a highest state being verified;
• based on a result of the bitscan operation, adjust the initial programming voltage for programming of subsequent wordlines;
• and
• in response to the result of the bitscan operation being failing, reduce a value of the initial programming voltage for programming of subsequent wordlines.

An apparatus, comprising:

• at least one memory block that includes a plurality of memory cells arranged in a plurality of word lines;
• a programming means for programming user data into the plurality of memory cells and configured to program the memory cells of the at least one memory block in a plurality of program loops, the programming means being configured to:
• perform a smart verify operation to acquire an initial programming voltage;
• perform a program operation on a selected wordline starting with the initial programming voltage;
• perform a bitscan operation of a highest state being verified;
• based on a result of the bitscan operation, adjust the initial programming voltage for programming of subsequent wordlines;
• and
• in response to the result of the bitscan operation failing, reduce a value of the initial programming voltage for programming of subsequent wordlines.