Enhanced IO interface for plc program and program-suspend-resume operations
AssigneeIntel NDTM US LLC
InventorsAliasgar S. Madraswala, Sagar Upadhyay
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AssigneeIntel NDTM US LLC
InventorsAliasgar S. Madraswala, Sagar Upadhyay
Estimating the term…
Methods and apparatus for Enhanced IO Interface for PLC program and program-suspend-resume operations. A NAND memory device includes blocks of single-level cell (SLC) memory and multi-level cell (MLC) memory storing n-bits per cell such as quad-level cell (QLC) or penta-level cell (PLC) memory. The NAND memory device further includes a plurality of page buffer latches and logic to copy data from a set of n SLC pages in a block of SLC memory into n respective page buffer latches and copy data from the respective page buffer latches to an MLC page (e.g., QLC or PLC page) in a block of MLC memory. These operations can be extended for NAND memory devices having multiple planes with blocks of SLC and QLC/PLC memory. QLC/PLC program and program-resume operations are supported with optional ECC correction operations.
A NAND memory device comprising:
A method, comprising:
A system, comprising:
Dependencies are inferred from the claim text.