Prediction unit with first predictor that provides a hashed fetch address of a current fetch block to its own input and to a second predictor that uses it to predict the fetch address of a next fetch block

A method, comprising:

• making, by a first prediction circuit, first predictions of information about fetch blocks of a program instruction stream, wherein a fetch block comprises a previously executed sequential run of instructions;
• and
• making, by a second prediction circuit, second predictions of information about the fetch blocks of the program instruction stream;
• wherein the first predictions are used by the second prediction circuit to make the second predictions;
• wherein the second predictions are made by the second prediction circuit with a higher prediction accuracy than the first prediction circuit makes the first predictions;
• and
• wherein a second misprediction penalty associated with a misprediction by the second prediction circuit is greater than a first misprediction penalty associated with a misprediction by the first prediction circuit.

A non-transitory computer-readable medium having instructions stored thereon that are capable of causing or configuring a microprocessor comprising:

• a first prediction circuit configured to make first predictions of information about fetch blocks of a program instruction stream, wherein a fetch block comprises a previously executed sequential run of instructions;
• a second prediction circuit configured to make second predictions of information about the fetch blocks of the program instruction stream;
• wherein the second prediction circuit is configured to use the first predictions to make the second predictions;
• wherein the second prediction circuit is configured to make the second predictions with a higher prediction accuracy than the first prediction circuit is configured to make the first predictions;
• and
• wherein a second misprediction penalty associated with a misprediction by the second prediction circuit is greater than a first misprediction penalty associated with a misprediction by the first prediction circuit.