Macro-op fusion for pipelined architectures
AssigneeSiFive, Inc.
InventorsAndrew Waterman, Krste Asanovic, Josh Smith
Life of this patent
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Abstract
Systems and methods are disclosed for macro-op fusion in pipelined architectures. For example, some methods include detecting a sequence of macro-ops stored in an instruction decode buffer, the sequence of macro-ops including a first macro-op, followed by one or more intervening macro-ops, followed by a last macro-op; determining a micro-op that is equivalent to the first macro-op combined with the last macro-op; and forwarding the micro-op to one or more execution resource circuitries for execution.
Claims20
An integrated circuit comprising:
- one or more execution resource circuitries configured to execute micro-ops to support an instruction set including macro-ops,
- an instruction decode buffer configured to store macro-ops fetched from memory, and
- an instruction decoder circuitry configured to:
- detect a sequence of macro-ops stored in the instruction decode buffer, the sequence of macro-ops including a first macro-op, followed by one or more intervening macro-ops, followed by a last macro-op, wherein the one or more intervening macro-ops include a conditional branch macro-op;
- determine a micro-op that is equivalent to the first macro-op combined with the last macro-op;
- and
- forward the micro-op to at least one of the one or more execution resource circuitries for execution.
A method comprising:
- detecting a sequence of macro-ops stored in an instruction decode buffer, the sequence of macro-ops including a first macro-op, followed by one or more intervening macro-ops, followed by a last macro-op, wherein the one or more intervening macro-ops include a conditional branch macro-op;
- determining a micro-op that is equivalent to the first macro-op combined with the last macro-op;
- and
- forwarding the micro-op to one or more execution resource circuitries for execution.
A non-transitory computer readable medium comprising a circuit representation that, when processed by a computer, is used to program or manufacture an integrated circuit comprising:
- one or more execution resource circuitries configured to execute micro-ops to support an instruction set including macro-ops,
- an instruction decode buffer configured to store macro-ops fetched from memory, and
- an instruction decoder circuitry configured to:
- detect a sequence of macro-ops stored in the instruction decode buffer, the sequence of macro-ops including a first macro-op, followed by one or more intervening macro-ops, followed by a last macro-op, wherein the one or more intervening macro-ops include a conditional branch macro-op;
- determine a micro-op that is equivalent to the first macro-op combined with the last macro-op;
- and
- forward the micro-op to at least one of the one or more execution resource circuitries for execution.
Dependencies are inferred from the claim text.