Flash memory cell structure having separate program and erase electron paths

A flash memory cell comprising:

• a well having a first-type dopant;
• a source having a second-type dopant and formed within the well;
• a drain having the second-type dopant and formed within the well;
• a floating gate above the well, wherein the floating gate has a first edge overlapping with the source and a second edge overlapping with the drain;
• a control gate above the floating gate;
• an oxide compound disposed between the floating gate and the control gate;
• a tunnel oxide disposed between the floating gate and the well,
• wherein the flash memory cell is configured, in one of a program mode or an erase mode, to move an electron from the source to the floating gate,
• wherein the flash memory cell is configured, in the other one of the program or the erase mode, to move an electron from the floating gate to the drain, and
• wherein the control gate extends around at least three sides of the floating gate, and wherein the oxide compound extends around at least three sides of the floating gate;
• and
• a first layer disposed on an opposite side of the well as the floating gate, the first layer having a second-type dopant to form a first p-n junction with the well to provide a diode.